X-bit labs

SiS755: New Chipset for Athlon 64 (page 2)

Category: Chipsets

by Ilya Gavrichenkov

[ 12/16/2003 | 11:25 AM ]

Since the memory controller in Athlon 64 systems has been moved to the central processor, the life of chipset developers has now become much easier. The engineers don’t have to bother about creating efficient memory controllers, but can focus on the improvement of the AGP interface, the system bus and the bus linking the two chipset Bridges.

SiS755 uses an exclusive 16-bit bidirectional MuTIOL 1G bus to connect the North and South Bridges of the chipset. It has been long and successfully used in SiS products. The key feature of this bus is its multiple streams support. That is, any bandwidth consumer can be allotted some portion of the total bus bandwidth. The MuTIOL 1G can also portion the bandwidth to several independent streams simultaneously. The peak bandwidth of the MuTIOL 1G is limited at 1.07GB/s.

SiS964 South Bridge coming with the standard version of the SiS755 chipset is the most advanced chip SiS has at its disposal today. The chip supports all the necessary interfaces and protocols, including two ATA/133 channels and two Serial ATA-150 ports. SiS964 allows uniting the SerialATA drives into RAID arrays of levels 0 or 1 as well as arranging them into a JBOD array. SiS964 also supports eight USB 2.0 ports, PCI bus, 10/100Mbit LAN MAC, six-channel AC’97 sound and so on. In fact, SiS964 only lacks IEEE1394 (FireWire) support. Some of the older South Bridges from SiS do support this interface, so the company might have just considered it not worth including into the basic specification of SiS755 solution.

The table below compares the characteristics of SiS755 with the functionality of the already announced chipsets from VIA and NVIDIA intended for the Athlon 64 platform:

	NVIDIA nForce3 150	VIA K8T800	SiS755
Processor bus	HyperTransport (8bit/600MHz upstream and 16bit/600MHz – downstream)	HyperTransport (16bit/800MHz upstream and 16bit/800MHz – downstream)	HyperTransport (16bit/800MHz upstream and 16bit/800MHz – downstream)
Processor interface	Socket 754
AGP	AGP 8x	AGP 8x	AGP 8x
South Bridge	-	VIA VT8237	SiS964
Bus between the chipset North and South Bridges	-	V-Link 8x (533MB/s)	MuTIOL 1G (1.0GB/s)
SerialATA-150	-	2 ports supporting RAID 0 and 1	2 ports supporting RAID 0andè 1
ATA-133	3 channels	2 channels	2 channels
USB 2.0	6 ports	8 ports	8 ports
IEEE1394	-	-	-
AC97	+	+	+
Ethernet	10/100Mbit MAC	10/100Mbit MAC	10/100Mbit MAC
PCI Masters	5	6	6

As we see, according to the formal specifications of SiS755, this solution looks much similar to VIA K8T800, save for the faster bus between the Bridges. Delving a little deeper, we may find some interesting things about SiS755, though. One of them is HyperStreaming architecture, which is a particular point of pride for SiS.

This architecture allows SiS to process the data streams inside the chipset North Bridge more efficiently. The architecture intellectually controls the data streams inside the chipset North Bridge, using advanced algorithms for conflicts arbitration. Processing a single stream, the architecture tries to minimize the latencies on the way. When there are several streams, special algorithms come into action to pipeline the transactions and perform them simultaneously. Besides that, the HyperStreaming architecture allows separating the streams into high-priority and ordinary ones, so some streams can get a reserved bandwidth portion for their needs.

Unfortunately, I cannot claim that this architecture is unique nowadays, since I don’t know what technologies VIA and NVIDIA use in their chipsets. Anyway, the tests you are going to see shortly prove that SiS755 does handle data more efficiently than the competitor products.

To wind up this section of the review, I would also like to tell you that SiS has already announced SiS755FX chipset which is going to add more nice things to the functions of the currently considered SiS755. I am talking about such things as support of 1GHz HyperTransport bus and Socket939 processors. This chipset is not demanded in the market yet, as there are simply no CPUs to use with it. SiS is evidently going to start mass shipments of this product a little later. As for the close-term outlook, we are expecting to see SiS760 soon. It is a SiS755-based chipset with the integrated graphics core aka Ultra256. SiS760 is going to be pin-compatible with SiS755. It will also be able to use either part of the system memory or a local frame buffer as the graphics memory.