EV7 processors could be connected to each other using various algorithms, but only the so-called "torus" and "shuffle" interconnects were implemented in real hardware. Also, the second one was more effective potentially in some situations (for example, considering 8-processor systems, "shuffle" allowed each processor to be connected directly to 4 others, while "torus" - to 3 other processors only). Of course, this difference didn’t matter any more in 12-processor systems.

This processor was manufactured with 7-layer 0.18µ CMOS8 process, consisted of 152 mln transistors (including 137 mln for I-cache, D-cache and S-cache), and therefore featured a very large die (397mm²). Prototypes were clocked at 1250MH (TDP of 155W), though those processors installed in systems produced by HP were running at 1000MHz to 1150MHz. From an engineering point of view, EV7 yielded significantly to the previous representatives of the Alpha architecture in terms of the density of functional units placed on the die. Of course, it affected the maximal core frequencies it could work at, the latencies of S-cache, and, hence, performance.

In December 2002, HP sent out a press-release saying that the first EV7-based servers would be available in January 2003. Later, EV79 would be produced (using 0.13µ SOI process), and this is when the Alpha architecture development should end. In March 2003 at ISSCC'2003 they presented a prototype of EV79 with a 251mm² die requiring 1.2V power, and clocked at 1450MHz (TDP of 100W). But in October 2003 some rumors about manufacturing difficulties sneaked out of IBM, and half a year later the processor was finally cancelled.

In August 2004, the last Alpha processor was announced. It was EV7z clocked at 1300MHz, manufactured with the same 0.18µ process. Like EV7, it was designed for HP's products only. They also mentioned that Alpha architecture based servers and workstations will keep selling under HP brand name until 2006, and will be supported until 2011, but no longer than that.

The cancelled 21464 (EV8) was supposed to be a successor to EV7, with twice as many primary functional units (8 integer and 4 floating-point pipelines) and 3MB S-cache. It was also supposed to support the new SMT technology (Simultaneous Multi-Threading), which implied a concurrent execution of up to 4 software streams inside a single core (maybe, this technology was related somehow to HyperThreading from Intel). The die manufactured with 0.13µ SOI process size equaled 420mm².