The PRISM Project

In the beginning of 1980s DEC was on the paramount of its financial wealth, mostly because of high revenues related to constantly growing sales of VAX machines. But nothing lasts forever, and it was obvious that some day VAX would have to leave the market in favor of a new architecture, like it was happening with PDP-11. Those days many companies started to pay more and more attention to RISC concepts and implementations, and DEC had no intention to ignore that trend. There were several subdivisions inside of DEC between 1982 and 1985, which researched actively over the RISC area:

• Titan, a high-speed design by Western Research Laboratory (DECwest) in Palo Alto (California), supervised by Forest Baskett, since 1982;
• SAFE (Streamline Architecture For Fast Execution), supervised by Alan Kotok and David Orbits, since 1983;
• HR-32 (Hudson RISC 32-bit), located at DEC's factory in Hudson (Massachusetts), supervised by Richard Witek and Daniel Dobberpuhl, since 1984;
• CASCADE by David Cutler in Seattle (Washington), since 1984.

In 1985, after Cutler's initiative on creating a "corporate RISC plan", all 4 projects were merged into one aka PRISM (Parallel Instruction Set Machine), and the first draft for a new RISC processor was released in August 1985. Here I would like to mention that DEC had participated in the development of MIPS R3000 processor those days, and even initiated the creation of Advanced Computing Environment consortium to promote that architecture into the market.

Therefore, no wonder that the developed processor inherited many features of MIPS architecture, but at the same time the differences were obvious. All instructions were of fixed-length of 32 bits, with the upper 6 and the lower 5 presenting an instruction code and the remaining 21 were reserved for immediate data or addressing needs. There were 64 primary 32-bit general purpose registers (MIPS implied 32 registers), also 16 additional 64-bit vector registers, 3 control registers for vector operations: two 7-bit (vector length and vector count), and one 64-bit (vector mask). There was no processor status register, that is why the result of two scalar operands comparison was placed into a general purpose register, while the result of two vector operands comparison - into the vector mask. There was no built-in floating-point unit. A set of special instructions (Epicode, or extended processor instruction code) was created in software, using loadable microcode, to facilitate handling of special tasks required by the environment or operating system, and not supported by the standard instruction set. Later on, this function was implemented for Alpha architecture under the name of PALcode (Privileged Architecture Library code).

In 1988, when the project was still in progress, DEC’s high management decided to close it, considering any further financial support a waste of money. Cutler protested against that decision, resigned and went to Microsoft, to supervise a department developing Windows NT.

In the beginning of 1989 DEC presented its first RISC-powered workstations. They were DECstation 3100 with 32-bit MIPS R2000 inside clocked at 16MHz, and DECstation 2100 using the same processor type but clocked at 12MHz. Both machines were running Ultrix OS, and were priced rather inexpensively (about 8,000 USD (in 1990) for DECstation 2100).