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The Alpha Project

In 1989, aging VAX architecture was hardly able to compete with 2nd generation RISC architectures, such as MIPS and SPARC, and it was quite obvious that the next generation of RISC hardware would leave not so many chances for VAX to survive. In the middle of 1989 DEC engineers received a task to create a competitive RISC architecture with long-term potential, but at the same time carrying a minimal set of incompatibilities with VAX, because VAX/VMS and all accompanying applications had to be ported to the new architecture. It was also defined to be 64-bit right from the start, since competitors were about to release their 64-bit solutions at about the same time. A development group was created, where Richard Witek and Richard Sites were the chief architects.

Alpha architecture was mentioned officially for the first time on February 25, 1992, during a conference in Tokyo. Also, most key features of the new architecture were listed within a concise overview (for comp.arch, a USENET conference). They also mentioned that "Alpha" was an internal codename, and an official name would be provided later. The new processor was of a clean 64-bit RISC design to execute fixed-length instructions (32 bits each), with 32 integer 64-bit registers, operated 43-bit virtual addresses (with a possibility to expand up to 64 bits in future implementations), and used, like VAX, little-endian byte order (i.e. when a low byte of a register occupies low memory address line unlike big-endian byte order, introduced by Motorola and used in most processor architectures, where a low byte of a register occupies high memory address line). A math1ematical coprocessor was built into the core, with 32 floating-point 64-bit registers using random access order, unlike primitive stack access order, implemented in Intel x87 coprocessors. The total lifetime of the new architecture was estimated as 25 years at least.

The instruction set was simplified to facilitate pipelining as much as possible, and consisted of 5 groups:

  • integer instructions;
  • floating-point instructions;
  • branching and comparison instructions;
  • load and store instructions;
  • PALcode instructions.

It should be mentioned that there were no integer division instructions, because they were most complex and thus badly pipelineable, so they were emulated.

Alpha architecture was a "real" RISC (unlike modern processors with i386 architecture, which are RISC only inside). The conceptual difference between RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) was (and still is) as follows:

Feature

CISC

RISC

Instruction
length

Variable,
depends on
the instruction type

Fixed,
doesn't depend on
the instruction type

Instruction
set

Wide,
adapted for programmer's
needs

Balanced,
adapted for processor execution
convenience

Memory
access

Allowed for different kinds
of instructions

Allowed for load/store
instructions only

The processor was supposed to be launched in production at a very high frequency - 150MHz, which should be increased up to 200MHz with the same production technology. This appeared possible due to successful architecture, as well as to engineers' decision to give up automatic design systems and to perform all the work manually.

The project entered the manufacturing stage, and was reorganized as a regular division of DEC very soon.

DEC's marketing department came up with a name for the new architecture, which was called AXP (or Alpha AXP), though no one knows for sure what exactly this abbreviation meant. Quite possible, nothing at all; in the past, DEC had legal problems with its VAX brand, because there was another company, a vacuum cleaners manufacturer, claiming this name, so the conflict was taken to court. By the way, thay also insisted that DEC's equipment sales suffered because of the other company's slogan, "Nothing sucks like a Vax!" After all, a joke appeared saying that AXP meant "Almost Exactly PRISM"

 
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