21064A (EV45) was announced at Microprocessor Forum in October 1993. It was a modified EV4, produced using 4-layer 0.5µ CMOS5 process. 21066A (LCA45) was presented at COMDEX'94 in November 1994. It was LCA4 modified almost the same way as EV4 towards EV45. Note that DEC's marketing people had developed a habit to add a letter to the processor model name after a redesign towards a more advanced technical process. In fact, the cores didn’t undergo any dramatic changes: I-cache and D-cache of EV45 got twice as big (16KB I-cache + 16KB D-cache), their data and tag fields gained a parity bit each, branch history fields of the I-cache were expanded to 16 bits, D-cache had become 2-way set associative, and 1-bit byte parity mode was added to those existing integrity modes of the system data bus. Also, both EV45 and LCA45 were awarded with a modified F-box. Namely the modifications touched upon the division optimization that implied that EV4 could execute commands with single-precision operands in 34 clocks and with double-precision operands in 63 clocks, with no dependence upon the operands values. As for EV45, it could do the same in 19-34 clocks for single-precision operands and in 29-63 clocks for double-precision operands, depending on the operands' values. LCA45 was also manufactured by Mitsubishi. Both die sizes were decreased to 164mm² for EV45 and 161mm² for LCA45. The transistors count increased to 2.85 mln for EV45, and remained the same for LCA45 (1.75 mln). Finally, power consumption per clock decreased for both processors, though voltage remained unchanged (3.3V). The core frequencies of EV45 were ranging from 200MHz to 300MHz (TDP from 24W to 36W), those of LCA45 - from 166MHz to 233MHz.

Since DEC developed equipment for the United States Department of Defense, 21068 66MHz and 21068A 100MHz were introduced in 1994. They were developed basing on LCA4 and LCA45 respectively, and were advanced for military needs (passive cooling, extreme temperature conditions, etc.).

First chipsets for EV4 supported TURBOchannel, FutureBus+, and XMI peripheral buses. Though all of them were high-speed designs for those days (about 100Mb/s per bus), they didn't get very widely spread, so only a very limited set of peripherals was available for them. Therefore, DEC paid special attention to industry-standard bus architectures, such as PCI and ISA (EISA). A new chipset was introduced in 1994, DEC Apecs, and it was available in two modifications: for 64-bit system data bus (21071), and for 128-bit system data bus (21072). They differed by the number of micro-chips: 21071 consisted of 4 chips (1 universal controller, 2 data slices, 1 PCI bus controller), while 21072 consisted of 6 (there were 2 additional data slices). They supported 33MHz system bus frequency, up to 16MB of B-cache, up to 4GB of FPM parity memory with access time from 100 to 50ns. Support for ISA or EISA buses could be implemented in the standard bridges, such as i82378IB (ISA) or i82378EB (EISA).

The first Alpha workstation was available in November 1992. It was DEC 3000 Model 500 AXP (codenamed Flamingo), with EV4 150MHz, 512KB of B-cache, 32MB of main memory, 1GB SCSI HDD, SCSI CD-ROM, built-in 10Mbit Ethernet controller (thick coaxial and twisted pair), built-in sound and ISDN controllers, also a 19" monitor (1280x1024 8-bit). The price was shocking: $38,995.