EV5, EV56, PCA56, PCA57

DEC unveiled the very first information about its 2nd generation Alpha processor on Hot Chips conference in Palo Alto (California), which started on August 14, 1994, although the official release of 21164 (EV5) dated back to September 7, 1994, when the respective DEC’s press-release was published. The processor was based on the EV45core, and was rather an evolution of the latter than a revolutionary new design. The number of pipelines was doubled, both integer and floating-point, compared to EV4 or EV45. Also, the floating-point pipelines were transformed to work in 9 stages instead of 10. But, the integer pipelines weren't all the same: while both were capable of elementary arithmetical and logical operations, the 1st could only multiply and shift, and the 2nd was only able to process conditional/unconditional jumps. Also, both pipelines could calculate virtual addresses for load instructions, but only the 1st could do the same for store instructions. The floating-point pipelines were different as well: the 1st could execute any floating-point code except for multiply instructions, which were the only code the 2nd pipeline could process. I-box was able to fetch and decode up to 4 instructions per clock, to provide the execution units with the necessary load. This processor was manufactured with the same 4-layer 0.5µ CMOS5 process as EV45, required 3.3V voltage, contained 9.3 mln transistors (including 7.8 mln for integrated cache areas), features a 299mm² die, which was very close to theoretical limits of the technical process involved. Core frequencies ranged from 266MHz to 333MHz (TDP from 46W to 56W). The processor was manufactured in IPGA-499 (Interstitial Pin Grid Array) form-factor.

I-cache and D-cache were sized and organized just like those in EV4, i.e. 8KB each. D-cache remained write-through, but it was made dual-ported, i.e. was able to deliver data for 2 load instructions per clock. Sacrificing transistors for the sake of performance, D-cache was composed physically of 2 absolutely identical parts 8KB each, so data could be read from either of them, but had to be written into both. The processor had 96KB of the integrated L2 cache (S-cache, secondary cache), write-back, 3-way set associative, so C-box knew to use it via a dedicated 128-bit data bus. At the same time, B-cache was also functional (though remained optional, consisted of external cache SRAMs, and could be as large as 64MB, though usually ranged from 1MB to 4MB). In other words, EV5 supported 3 cache levels! S-cache could be accessed via a 4-stage pipeline: two clocks for tag search and modification, and two clocks for data access and delivery. Every S-cache line was 64 bytes wide (though it could also be addressed as two sub-lines, each 32 bytes wide), and had one tag per line. D-cache read latencies were reduced to 2 clocks, and S-cache could deliver data in 7 clocks (as I have mentioned above, 4 clocks for the first 16 bytes, and 1 clock for every next 16 bytes to fill the entire line). Like in EV4, the contents of D-cache was duplicated, although this time in S-cache. Besides, B-cache was made including S-cache, regardless the associativity differences. I-TLB held 48 entries (for pages sized from 8KB to 4MB), D-TLB - 64 entries, and it became dual-ported like D-cache. The system data bus featured fixed-length of 128 bits (with additional 16 bits for ECC protection), and still multiplexed with the data path to B-cache. The system address bus was 40 bits wide, the control bus was a 10-bit one.