21164A (EV56) was introduced at Microprocessor Forum, in October 1995. It was a modified version of EV5, after a technology shrink to 0.35µ CMOS6, manufactured at the same factory in Hudson (DEC had invested about 450 mln USD in modernization of this facility). The most important architectural difference was BWX (Byte-Word Extension) - a set of 6 additional commands to load/store data in 8- or 16-bit quanta. At first, Alpha architecture was forced to load/store data in 32- or 64-bit quanta, which caused certain difficulties for porting or emulating code from other processor architectures, such as i386 and MIPS. A request to implement BWX in hardware was submitted in June 1994 by Richard Sites, and was approved in June 1995. Note that BWX required both, the processor and the chipset, to support it. EV56 was designed to work at core frequencies ranging from 366MHz to 666MHz (TDP from 31W to 55W), starting from the summer of 1996. Samsung also produced EV56 according to a license agreement signed in June 1996 (a 666MHz version was shipped by Samsung only). It contained 9.66 mln transistors, featured 209mm² die, and required dual voltage (2.5V for primary and 3.3V for input-output circuits).

21164PC (PCA56) was introduced on March 17, 1997. It was a low-cost version of EV56, designed jointly by DEC and Mitsubishi. S-cache and the accompanying logic were absent, but I-cache grew twice as big (16KB). The processor consisted of 3.5 mln transistors, and its die was 141mm² big. It was manufactured with the same technical process and required the same voltage as EV56. The form-factor did change, however: the newcomer was designed as IPGA-413 instead of IPGA-499. Its core frequencies ranged from 400MHz to 533MHz (TDP from 26W to 35W). Later on, Samsung also manufactured a 0.28µ 21164PC (PCA57), with twice as big I-cache and D-cache and with 2-way set associativity of the D-cache. The transistors count increased to 5.7 mln, but the die size decreased to 101mm². It required lower voltages: 2.0V for primary and 2.5V for input-output logic. The supported core frequencies lay between 533 and 666MHz (TDP from 18W to 23W).

Besides the BWX instructions inherited from EV56, PCA56 supported a new set, MVI (Motion Video Instructions), intended to accelerate video and audio calculations using SIMD (Single Instruction - Multiple Data) approach, somewhat comparable to MMX.

The first standard chipset, developed for EV5, was DEC Alcor (21171). It supported 33MHz system bus, up to 64MB of B-cache, up to 8GB of FPM ECC memory (using 256-bit wide memory bus), and 64-bit PCI bus (33MHz). The ISA or EISA bus support could be implemented in the standard bridge, as usual. There was no built-in IDE controller (could be installed separately, using a third-party chip). The chipset consisted physically of 5 chips: 1 universal controller (including PCI bus support), and 4 data switches. Together with the beginning of EV56 production, they released a new modification of Alcor, which acquired BWX support. It was Alcor 2 (21172). The next member of this chipset dynasty was Pyxis (21174), a single-chip solution supporting 66MHz system bus and 66MHz SDRAM ECC memory (although, using 128-bit memory bus). For PCA57-based systems they also developed VLSI Polaris chipset.