Articles: CPU

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The restrained optimism about the 90nm+SOI technology is due to the fact that AMD has already showcased an operational prototype of the Opteron made with it, although the CPU had a small frequency, only 800MHz. The company has enough time until Q3 to polish this technology off, if no principal troubles arise. For example, Intel encountered the problem as its 90nm+”strained silicon” technology produced unexpectedly high (higher, than predicted by the theory) leakage currents. As a result, chips made with this tech process heat up much more than the previous core. AMD uses another variation of the technology, which doesn’t have problems with leakage currents, but has other drawbacks. For example, it is poorer at scaling up with the frequency; moreover, it potentially has problems with temperature distribution inside the processor. Anyway, only practice will give us the definite answer. If everything goes right, we’ll see an abundance of new processors for the Socket 754 and Socket 939, manufactured by the 90nm+SOI technology.

This transition should drop the die manufacturing cost significantly (the square of the new die will be 102 sq. mm instead of 193 sq. mm) – another aid in the competition with Intel. This is the more important as Intel has already practically finished its transition to 90nm and also has 300mm wafers, which themselves reduce the cost of the processor.

AMD also published the maximum heat dissipation for the Socket 939 – 105W. Considering that this number refers to the entire lifecycle of this socket, we have a reason to be optimistic. At least, this is much smaller than the maximum heat dissipation of the Prescott platform for the LGA775 (up to 120W) and Tejas (around 150W). Thus, this technology will probably allow reaching 2.8-3.0 frequency (although not in the first revision of the processor). This would give us a 4000+ or 4300+ model in the AMD nomenclature. Besides that, the new core may support SSE3 (in fact, besides Hyper-Threading-related instructions, nearly all other instructions have long had functional analogs in Extended 3DNow!; their support means only “teaching” the decoder to transform them into internal macro-ops). Of course, save for MWAIT and MONITOR instructions that refer to Hyper-Threading – the Athlon 64 doesn’t need them. We’ll probably also see support of DDR2 memory. However, the use of such memory will require new mainboards and a new processor form-factor.

By the way, the new core (Newcastle) may come manufactured with the current 130nm+SOI technology, with 512KB of cache. Even this variant is relatively profitable since allows reducing the die surface to 150 sq. mm, which tells favorably on the processor self cost. It would also be positive for AMD’s profits and the company needs money, considering the construction of the new Fab35. This is probably an escape way in case there are problems with implementation of 90nm+SOI. The transition to the intermediary core will allow increasing the CPU output by one third from the same amount of wafers.

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