X-bit labs

AMD: Per Aspera Ad Astra (page 4)

Category: CPU

by Victor Kartunov

[ 03/31/2004 | 06:54 AM ]

The gains from a faster, “overclocked” bus will be more conspicuous for multi-processor mainboards for Opterons due to the features of the architecture of Opteron-based multiprocessor systems. All inter-processor communication is performed through HyperTransport busses – by making this bus faster we make data transfers faster and reduce latencies. Opteron-based systems would become “flatter” for the OS – it would take about the same time to access the processor’s own and the other processor’s memory. This effect (flattening of the memory space) will be visible when the bandwidth of the HyperTransport bus exceeds the memory bandwidth for each processor. In this case, the Opteron-based architecture will reach the highest efficiency. Moreover, the faster the inter-processor bus is, the better the system scales up with the number of processors. In ideal, the bandwidth of the inter-processor busses should be enough for transferring all requests to memory from all processors. That is, the bus bandwidth should ideally be equal to the total memory bandwidth of all processors. Today, two-processor systems need 12.8GB/s (that’s enough for the processors to read data from the memory belonging to the other processor at full speed). It is harder to make this estimate for 4-processor systems due to different routes the request may take. An approximation tells us that a triple memory speed should be enough. In other words, the number is somewhere around 20GB/s (we suppose that the memory bandwidth = 6.4GB/s, corresponding to dual-channel DDR400 SDRAM).

Now, let us recall AMD’s having recently announced the new HyperTransport standard, version 2.0. Its distinguishable features are support of compatibility with the PCI Express (that’s reasonable since the industry will surely embrace the new peripheral bus – the PCI is not enough for many modern devices) and new speeds. The maximum speed looks most curious: 22.4GB/s! Once again we have a strange coincidence? Well, let’s not be paranoid. Current systems use a 16-bit-wide bus with a twice lower speed and that’s enough for a two-processor machine – it becomes quite flat for the OS with respect to the access times to the processor’s own and the other processor’s memory.

It’s probable that AMD will build an etalon system around the new bus version (this would be most interesting for four- and eight-processor systems) – the performance growth will cover the cost of its development. This also will require that the new version of the HyperTransport bus is supported by processors. I won’t be surprised to find that one of the next steppings of the Opteron (Athlon 64) has an undocumented support of this bus. This support may even have been already included into the recently released CG stepping.

Anyway, this is rather a distant future, while now we’re going to see a trivial but so pleasant acceleration of the HyperTransport to 1GHz. This fact is nice as it is, but the first generation of Opteron-supporting mainboards is surely not intended for any acceleration of the HyperTransport. This problem may have a solution like BIOS upgrade – specific situation will depend on the manufacturer of the clock and the “reliability reserve” of the bus wiring on the PCB. I think that the platforms were originally designed with some reserve for the bus to be noise-tolerant. However, we can’t deny or accept this supposition. By the way, if the base frequency remains the same, it’ll be easier – it shouldn’t be a problem to change the multiplier coefficient. For example, one of the first Opteron-supporting mainboards from Arima already supports this bus frequency.

Let’s summarize: introduction of a faster bus brings huge dividends, both technological and marketing. The lifecycle of the platform will be longer due to its better characteristics. The acceleration of the HyperTransport bus has been rumored by various news agencies recently – there is no smoke without a fire.