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Inside Ontario and Zacate

X-bit labs: I wonder whether you can describe how the two x86 cores and stream processing cores are connected between each other, what's the total bandwidth that you have inside the core, whether the GPU essentially sits on an internal PCI Express bus and so on?

Godfrey Cheng: There is an internal bus that we call common core interface, which is quite similar to PCI Express, but it is not just an internal PCI Express. It is a very efficient interface between the two cores.

X-bit labs: So, can we expect you to continue using that common core interface in future products?

Godfrey Cheng: Because we are not making a public specification, we have the ability to optimize the interconnects as compute loads or as programs change. What we chose for Llano and Ontario/Zacate might be very much different for the next generation. We are not going to physically recreate PCI Express as a proprietary spec internally, but we are going to optimize the interface as much as we can.

X-bit labs: All Evergreen graphics processors have pretty complex architecture of internal caches. Was this architecture inherited from Cedar chip, or does the GPU use the L2 cache of CPU cores?

Godfrey Cheng: When we integrated our discrete-level GPUs into APUs, we took the best what we had to offer from our graphics processing units, so, fundamental architecture and cache architecture are the same as in the standalone family. It really does not make sense for us to start reinventing the cache for our built-in GPUs because quite frankly our GPUs are world-class and that is not something we need to innovate.

 
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