X-bit labs

AMD K10 Micro-Architecture

Category: CPU

by Yury Malich

[ 08/17/2007 | 10:06 AM ]

First AMD Barcelona processors should be announced in a month already. They will be the first solutions to be built on AMD’s new K10 micro-architecture that the company pins a lot of hopes upon. Let’s take a closer look at the micro-architectural innovations that will be introduced in these new solutions.

Table of contents:

• Introduction
  
• Instructions Fetch
  
• Branch Prediction
  
• Decoding
  
• Sideband Stack Optimizer
  
• Instruction Control Unit
  
• Integer Execution Unit
  
• Floating Point Unit
  
• Memory Subsystem
  
• Load/Store Unit
  
• L1 Cache
  
• L2 Cache
  
• L3 Cache
  
• TLB
  
• Memory Controller
  
• Prefetch
  
• New Instructions
  
• Virtualization
  
• Power and Frequency Management
  
• Conclusion
  

Introduction

AMD promises to introduce its new quad-core processors with K10 micro-architecture in the end of August – beginning of September this year. The first processors on this new micro-architecture will be server Opteron chips based on a core codenamed Barcelona. Unfortunately, AMD engineers failed to hit mass production quantities with the current revision of high-frequency chips. Looks like the main obstacle on the way to higher working frequencies was the fact that four cores running at high speed consume much more power than the platform TDP actually allows. With every new revision and transition to finer production technologies the power consumption will keep lowering and the working frequencies will keep growing. So far, AMD has to immediately start selling processors in order to improve its financial situation, so the first one to start selling will be the quad-core server processor model working at 2.0GHz.

In Q4 2007 AMD promises to increase Opteron working frequencies up to 2.4-2.5GHz and release desktop processors on K10 micro-architecture:

• Phenom FX (codenamed Agena FX) – 4 cores, 2MB L3 cache, clock frequencies starting at 2.2-2.4GHz, AM2+ Socket, F+;
• Phenom X4 (codenamed Agena) – 4 cores, 2MB L3 cache, clock frequencies starting at 2.2-2.4GHz, AM2+ Socket.

Later in early 2008 AMD promises to introduce “lite” modifications of their new processors, such as:

• Phenom X2 (codenamed Kuma) – 2 cores, 2MB L3 cache, clock frequencies starting at 2.2-2.6GHz, AM2+ Socket;
• Athlon X2 (codenamed Rana) – 2 cores, no L3 cache, clock frequencies start at 2.2GHz, AM2+ Socket;
• Sempron (codenamed Spica) – 1 core, clock frequencies start at 2.2-2.4GHz, AM2+ Socket.

But this is all in the future. So far let’s take a look at the innovations introduced in the new AMD micro-architecture. In our today’s article I am going to try and reveal all the new architecture details and see what practical value they will have for us.