Articles: CPU
 

Bookmark and Share

(24) 
Pages: [ 1 | 2 | 3 | 4 | 5 | 6 | 7 ]

Conclusion

The future processor from AMD, currently known as K8L, will be the next step in the evolution of the K8 series. The improvements we learned about so far such as increased to 32 bytes instruction sample, improved branch prediction algorithm, introduction of out-of-order reading, will eliminate a few bottlenecks and improve the integer performance. The expansion of SSE instruction sets will help improve the performance significantly in applications dealing with heavy floating-point or integer calculations using SSE instructions, where K8L will be able not only to compete successfully but even to outperform Conroe. The inability to decode and retire 4 commands per clock cycle in some cases may result into tangible performance gaps in integer applications. However, it may not be of that much importance in most cases, because the typical instruction execution pace in real integer applications does not exceed 2-2.5 instructions per cycle because of the data dependence. K8L performance may also be increased in other ways without raising the number of decoding and retirement pipes. Here I am talking about increasing the scheduler queue depth, reducing the number of false dependences (thanks to mechanisms similar to stack engine) and performing out-of-order reading skipping the writes. We do not know today if AMD will be able to implement these features in their new processor. We also do not know if they will modify the caching and prefetch system. However, this is very important for successful competition of the new K8L against Conroe processor in the entire range of tasks.

The successors to K8 architecture require a lot of work. They need not just to compete with Intel solutions, but to outperform them, and that is why their architecture needs to be free from the K8 bottlenecks and has to be able to decode and process up to four instructions per clock. Alas, developing and perfecting a new core is a tremendously laborious and time-consuming task. Even if a new architecture is under development at AMD, it will hardly become market-ready in the next couple of years. It’s hard to tell what this rapidly developing industry will have become like by that time!

The author would like to thank the following people:

Yan Keruchenko aka C@t - for constructive criticism and help with theoretical analysis
Sergey Zagursky aka McZag and Sergey Romanov aka GReY - for constructive criticism, valuable hints and suggestions
Maria Desyatnikova - for editorial help
 
Pages: [ 1 | 2 | 3 | 4 | 5 | 6 | 7 ]

Discussion

Comments currently: 24
Discussion started: 08/24/06 02:35:28 PM
Latest comment: 01/18/07 05:53:49 PM

View comments

Add your Comment




Latest materials in CPU section

Article Rating

Article Rating: 9.2066 out of 10
 
Rate this article:
Excellent
Average
Poor