Articles: CPU

Bookmark and Share

Pages: [ 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 ]

HyperTransport 3.0

Together with a few changes in the core micro-architecture, AMD engineers paid special attention to modifying the interfaces Phenom CPUs use to communicate with the rest of the world. First of all I would like to point out faster HyperTransport bus that meets specification version 3.0 in the new processors. While Athlon 64 processors used HyperTransport bus with 8GB/s bandwidth, Phenom may exchange data with the chipset at 14.4-16.8GB/s speed. Moreover, HyperTransport 3.0 spec also allows to additionally increase the bus bandwidth to 20.8GB/s, which will evidently be implemented in the upcoming quad-core processors.

Faster bus between the processor and the chipset may also be important for those systems where multiple graphics cards are installed. That is why HyperTransport 3.0 support became one of the primary distinguishing features of the Spider platform. This new platform supports Crossfire configurations built with two, three and four graphics accelerators.

At the same time, HyperTransport protocol versions are backward compatible, so you can use Phenom processors in old mainboards built on chipsets supporting only the previous HyperTransport 2.0 bus.

However, we shouldn’t overestimate the importance of HyperTransport 3.0 bus support in the new Phenom processors. Since AMD CPUs feature an integrated memory controller, the bandwidth of the bus between the CPU and the chipset matters only in “heavy-duty” graphics applications.

New Memory Controller Features

As for the memory controller, it also got a few things improved in the new Phenom processors. Although new AMD CPUs, continue working with DDR2 SDRAM, just like their predecessors, AMD engineers provided Phenom with DDR2-1066 modules support, as well. However, in order to meet JEDEC standards, DDR2-1066 memory can only work in Phenom platforms with pretty “weak” timings of 4-5-5-15 or higher.

The second peculiarity of the integrated memory controller is the fact that it is implemented as two independent 64-bit controllers rather than a single 128-bit interface. This allows the memory of Phenom platforms to work in two modes: ganged and unganged. The first one is analogous to the usual 128-bit dual-channel mode. The second one implies that the CPU can deal with two independent 64-bit memory controllers thus processing two memory requests simultaneously, which is good for multi-threaded environments.

Phenom memory controller is also interesting because it runs at a different frequency than the CPU clock: it uses its own clock frequency multiplier and runs at 2GHz on all currently available CPU models. They did it this way to ensure that the actual memory frequency always matches the desired one, which was not always the case with previous generation AMD processors. They frequency was obtained by applying integer dividers to the CPU clock speed value. So, the Phenom memory controller may set the DDR2 SDRAM frequency at exactly 400, 533, 667, 800 or 1066MHz at any clock speeds.

Even More Energy Efficient: Cool’n’Quiet 2.0

Cool’nQuiet technology in Phenom processors got to a completely new level, too. Now they call it Cool’n’Quiet 2.0. It allows to independently adjust the power consumption and frequency of all four processor cores and memory controller.

Moreover, Phenom also supports C1E state that takes place for the processor after a few milliseconds of idling. In this case the CPU not only drops down its clock speed, but also reduces the HyperTransport and system bus power consumption.

Another new and pretty interesting feature of the Cool’n’Quiet 2.0 technology is the ability of the CPU voltage regulator to receive data on the current power-saving CPU mode. Theoretically, it allows adjusting the voltage regulator circuitry parameters interactively depending on the processor operational conditions. I believe that mainboard developers will be able to implement corresponding algorithms in their solutions.

Pages: [ 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 ]


Comments currently: 94
Discussion started: 12/20/07 11:29:54 AM
Latest comment: 05/20/08 12:39:59 AM

View comments

Add your Comment