Articles: CPU
 

Bookmark and Share

(47) 
Pages: [ 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 ]

Besides the support of dual-channel memory access, the AMD engineers improved the memory controller of Socket 939 CPUs for better compatibility with different memory modules. They introduced a special 2T DRAM Timing, which lowers the bar the memory controller of the Athlon 64 sets for DDR SDRAM modules. Thanks to that, the Socket 939 Athlon 64 can work with four memory modules in the DDR400 SDRAM mode. You should be aware, though, that the highest performance, with the most aggressive 1T timing, is only achievable when you plug in a couple of identical DDR400 SDRAM modules. When four memory modules are in use, the memory controller of the Athlon 64 can only support DDR400 SDRAM with the slower 2T timing. Moreover, if the four installed modules are two-sided, the speed of the memory subsystem will be dropped to DDR333 even with 2T timing.

We carried out a brief test session to check out the influence of the 2T timing on the performance, using a new Socket 939 Athlon 64 3500+ processor (2.2GHz, 512KB L2 cache). Its memory subsystem worked with DDR400 SDRAM (2-3-2-6), the DRAM Timing being set to 1T and 2T. We left the rest of the memory subsystem settings identical in this test:

1T DRAM Timing

2T DRAM Timing

Sandra 2004, Memory Bandwidth Int, MB/s

5906

4900

Sandra 2004, Memory Bandwidth Float, MB/s

5832

4900

Sciencemark 2.0, Memory Bandwidth, MB/s

5692.29

4525.71

Sciencemark 2.0, Memory Latency, cycles

96

107

PCMark04, Overall score

4525

4438

PCMark04, CPU score

4178

4134

PCMark04, Memory score

5392

4734

Quake3 (four), 1024x768

419.3

403.1

Unreal Tournament 2004 (dm-rankin), 1024x768

112.33

108.52

Far Cry, 1024x768

68.65

68.26

As you see, DRAM Timing is an important parameter, affecting the overall performance of the system. The owners of Socket 939 systems should pay attention to the fact that the use of more than two memory modules may bring about a performance reduction.

The memory controller is not the only thing that changed with the transition to Socket 939. Athlon 64 processors have acquired a faster HyperTransport bus, which can now work at frequencies up to 1GHz, providing a 25% bandwidth growth. Thus, the bandwidth of the HyperTransport bus in Socket 939 systems is now 4GB/s, into each direction. On the other hand, this acceleration of HyperTransport is unlikely to bring any serious profits, because all the busses attached to the chipset don’t sum up to match this gigantic bandwidth. This is confirmed by the results of the mini-test we carried out with an Athlon 64 3500+, using 1GHz and 800MHz HyperTransport.

1000MHz HyperTransport

800MHz HyperTransport

PCMark04, Overall score

4525

4526

PCMark04, CPU score

4178

4173

PCMark04, Memory score

5392

5393

Quake3 (four), 1024x768

419.3

419.2

Unreal Tournament 2004 (dm-rankin), 1024x768

112.33

112.31

Far Cry, 1024x768

68.65

68.56

The two versions of the HyperTransport bus show nearly the same performance. The difference between them fits into the measurement error range. Thus, I can’t say the acceleration of the HyperTransport is in any way profitable to current computer systems. Some advantages may show up on the transition from the AGP 8x to the PCI Express x16 interface. Having dedicated read and write channels, the PCI Express x16 may provide a total bandwidth of up to 8GB/s as HyperTransport bus that works at the 1GHz frequency.

Talking about the HyperTransport bus, I should note that Socket 939 processors, unlike their Socket 940 mates, are not supposed to work in multiprocessor systems, because they have only one HyperTransport link, to the chipset.

 
Pages: [ 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 ]

Discussion

Comments currently: 47
Discussion started: 06/01/04 12:31:35 AM
Latest comment: 11/30/07 03:06:20 PM

View comments

Add your Comment