Athlon 64 X2 Architecture
I would like to point out that the implementation of dual-core design in AMD processors is different from what we have seen by Intel. Although Athlon 64 X2 is actually a combination of two Athlon 64 processors in a single piece of silicon, the way these cores communicate in a dual-core solution from AMD differs from what Intel offered in its Pentium D and Pentium Extreme Edition.
The thing is that Intel simply placed two Prescott cores into a single chip. In this case, the CPU has no special mechanisms for communication between the cores. In other words, the Smithfield cores communicate (to solve the cache coherency problems, for instance) via a system bus, just like the two CPUs in dual-processor Xeon based systems. As a result, the system bus is also shared by the processor cores when they work with the memory, which leads to higher latencies when both cores have to address the system memory.
AMD engineers kept in mind the future dual-core designs when they started working on the AMD64 architecture already. Therefore, dual-core Athlon 64 X2 processors managed to avoid a few bottlenecks. Firstly, far not all the resources are duplicated in the new AMD processors. Although each of the two Athlon 64 X2 cores features its own set of execution units and individual L2 cache memory, the memory controller and the Hyper-Transport controller are the same for both cores. The two cores communicate with the shared resources via the special Crossbar-switch and System Request Queue. The communication between the cores is organized on the same level that is why cache coherency issues can be resolved without loading the system bus and the memory bus.
This way the only remaining bottleneck of the Athlon 64 X2 architecture is the memory subsystem bandwidth of 6.4GB/s, which is shared by the two processor cores. However, AMD is planning to switch to faster memory types next year. In particular, they are going to be using dual-channel DDR2-667 SDRAM. This should have really positive influence on the dual-core processors performance in particular.
The new dual-core processors do not support contemporary types of memory with high bandwidth because AMD was trying to retain the compatibility of the new Athlon 64 X2 with the today’s platforms. As a result, the new processors can be used in the same mainboards as the regular Athlon 64 solutions. That is why Athlon 64 X2 are designed in Socket 939 package, feature dual-channel memory controller supporting DDR400 SDRAM and work with Hyper-Transport bus at 1GHz frequency. So, the only thing you will need to ensure that your Socket 939 mainboard supports the new AMD CPUs will be the BIOS update. Here I have to stress that AMD engineers were lucky to fit the power consumption of their new Athlon 64 X2 into the already set requirements.
So, the new AMD dual-core processors appeared better compatible with the already existing infrastructure than their Intel competitors. Intel's dual-core Smithfield based processors are compatible only with the new i955X and NVIDIA nForce4 (Intel Edition) chipsets and require more powerful voltage regulator on the mainboards.
Athlon 64 X2 processors are based on the Toledo and Manchester cores with E stepping, i.e. their functionality is similar to that of the Athlon 64 processors on San Diego and Venice cores (except for the ability to process two computational threads simultaneously). Athlon 64 X2 also supports SSE3 instructions and features an enhanced memory controller. Among the peculiarities of the memory controller of the new Athlon 64 X2 I would like to mention the support of different memory DIMMs in different channels (it even allows installing memory modules of different capacity in different channels) and the support of up to four double-sided DIMMs in DDR400 mode.
Athlon 64 X2 (Toledo) processors featuring two cores with 1MB of L2 cache memory per core consist of about 233.2 million transistors and are 199sq.mm big. So, as we have actually expected, the die size and the complexity of the dual-core CPU appeared almost twice as big as the die of a single-core processor.