Cache and Memory Subsystem

We have already paid due attention to the cache structure and memory subsystem organization in our extensive theoretical article devoted to the new processor core (see our article called Intel Prescott: One More Willamette-like Slow Processor or a Worthy Piece?). However, it is evident that disabled three fourths of the L2 cache should somehow tell on the characteristics of the cache memory subsystem by the new Celeron D processors. Let’s compare the L2 cache of the new Celeron D with that of Pentium 4 CPU based on Prescott core:

Intel Celeron D

Intel Pentium 4 (Prescott)

In other words, the smaller L2 cache of the Celeron D processor brought the number of associativity zones to four. As you remember, Celeron based on Northwood core features only two associativity zones. This way, the cache memory of the new Celeron D theoretically is not only larger, but also better organized than that of Celeron (Northwood).