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Weak Link: Clarkdale Memory Controller

Dual-die structure of the new Clarkdale processor is very interesting and quite justified. By distributing the functionality of a highly-integrated processing unit between two semiconductor dies put into the same packaging Intel engineers ended up with a solution that was inexpensive to make and suitable not only for the mainstream but also for the low-end segment. However, this lowering of the price point may produce some serious technical issues. In Clarkdale’s case we are mostly concerned with the fact that its integrated memory controller became not so integrated after all, which may affect the work of this CPU with the memory.

Although the memory controller is inside the processor packaging it doesn’t put it any closer to the CPU cores. In Clarkdale it is singled out into a separate semiconductor die together with the GPU. It is certainly great for improving the performance of the integrated graphics core that can use fast memory access, but at the same time the memory controller is separated from the computational cores. As a result, processor cores work with the memory not directly, but via QPI bus that connects the CPU and GPU dies within Clarkdale packaging.

What does it mean in practical terms? For our initial checkup we decided to use synthetic benchmarks to compare the performance of the memory subsystem in Core i5 LGA1156 processors from Lynnfield and Clarkdale families. The memory controller in the first processor is located inside the same die as the processor computational cores, that is why it doesn’t require any intermediate busses to work with the memory. The second processor has a “remote” memory controller that requires a pretty long chain including the following knots: core – QPI controller – QPI bus – QPI controller – memory controller. During the test both processors were launched at the same frequency of 2.8 GHz. The memory in both cases worked as DDR3-1333 SDRAM with 9-9-9-27 timings.

The first benchmark we used was Cachemem from the diagnostic Everest Ultimate 5.30 utility.


Lynnfield 2.8 GHz


Clarkdale 2.8 GHz 

The results turned out quite sad to put it mildly. Clarkdale loses about 25% to Lynnfield in practical memory subsystem bandwidth. Things look even worse for the new processor in terms of latency: the difference reaches 45%. Unfortunately, we seem to be paying too high of a price for lowering the processor production costs by separating the key functional units in two different semiconductor dies.

We arrive at the same sad conclusion after running the tests in another utility that measures the practical parameters of the memory subsystem – MaxxMem. And that is still the case even though we picked the junior Lynnfield processor, Core i5-750, to compare against Clarkdale, as it has the slowest memory controller working at 2.13 GHz instead of 2.4 GHz.


Lynnfield 2.8 GHz


Clarkdale 2.8 GHz

I have to say that the pseudo-integrated memory controller inside Clarkdale processor proved so slow that its performance could be compared to that of the controller in LGA775 systems using FSB bus to connect it with the CPU. Look, for instance, at the Cachemem results taken off the LGA775 system using DDR3-1333 SDRAM with 9-9-9-27 timings and built with Intel P45 chipset and Core 2 Quad Q9550 processor.


Yorkfield 2.83 GHz

The memory sub-system in LGA775 platform demonstrates even lower latency than the memory in Clarkdale based one! So, the idea to separate the processor cores and the memory controller in two different dies even located inside the same packaging resulted in very negative consequences for the memory subsystem performance. It has eventually dropped to the level we saw in systems with outdated structure (when the North Bridge was a separate chip).

The above described problems are also aggravated by the fact that Clarkdale's memory controller reacts a little strange to the use of lower memory timings. We failed to set CAS Latency to 7 on any of the three LGA1156 mainboards from Intel, Gigabyte and Asus built around H55 and P55 chipsets. When we selected the corresponding option in the BIOS Setup, nothing happened and the system still worked with CAS Latency 8 or 9. I hope that this isn’t a global restriction imposed by the Clarkdale memory controller, but simply a local issue that should eventually be fixed in new BIOS versions and mainboard revisions.

In this respect it is a little comforting that Clarkdale processors still have enough L3 cache memory. Even though it is only half the size of what Lynnfield CPUs have, it is in the same die as the computational cores. Therefore, if we go back to the results of Cachemem test, we will notice that it works not any slower than in Lynnfield demonstrating at even higher write speed.

 
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