X-bit labs

Getting Ready to Meet Intel Core 2 Duo: Core Microarchitecture Unleashed (page 5)

Category: CPU

by Ilya Gavrichenkov

[ 06/29/2006 | 05:13 PM ]

Intel Advanced Digital Media Boost

A separate approach to Core Microarchitecture improvement implied the modification of the SIMD instruction units (SSE, SSE2, SSE3). Contemporary software, for such application fields as image, video and sound editing, data encryption, scientific and financial tasks, uses a lot of SSE instructions that support all sorts of 128-bit operands (vectors and integers as well as high-precision real values).

This mere fact pushed Intel engineers to think about ways to speed up processor SSE units, especially since today’s Intel processors can only process one SSE instruction working with 128-bit operands within two clock cycles. They use the first clock cycle to process the first 64bits, and the second clock cycle to process the second 64bits. The new Core microarchitecture will make SSE instructions processing twice as fast as it used to be. Future CPUs will feature 128bit SSE units, so that the amount of data the CPU can handle per clock cycle will increase. Especially in that tasks that use a lot of SIMD instructions, such as various multimedia applications, for instance.

Besides speeding up the SIMD instruction execution units, Intel has once again revised the SSE command system. As a result, the SSE3 instructions set acquired 8 new commands. In fact, this SSE3 instructions extension has been planned since the times of Tejas processors. However, since they were cancelled, this modification found its way into new Core Microarchitecture.