X-bit labs

Getting Ready to Meet Intel Core 2 Duo: Core Microarchitecture Unleashed (page 6)

Category: CPU

by Ilya Gavrichenkov

[ 06/29/2006 | 05:13 PM ]

Intel Advanced Smart Cache

Since Core Microarchitecture is designed for dual-core right from the start, the developers could optimize some functional units according of the upcoming processors accordingly. Unlike all other desktop processors available these days, CPUs with Core Microarchitecture will share their L2 cache between the cores. This cache memory works similarly to the mechanisms that you can find in today’s dual-core Intel Core Duo mobile processors.

There are a few evident advantages of this approach to cache-memory implementation. Firstly, the CPU and flexibly adjust the size of the cache parts used by each core. In other words, any of the two cores of the Core Microarchitecture based CPU can get the entire L2 cache at its disposal, especially when one of the cores is idle. If both cores work at the same time, the cache memory is split proportionally depending on the frequency of requests sent by each core to the memory. Moreover, if both cores work synchronously with the same data, this data will be stored only once in the shared L2 cache memory. In other words, the shared intellectual L2 cache of the Core Microarchitecture processors is much more efficient and even much more capacious than two separate caches assigned to each core.

Shared cache memory may be very useful for dual-core processors in some other cases also. Take, for instance the current discussion of Core Multiplexing Technology that indicates that Intel engineers are ready to offer their solution for dynamic disabling of the second processor core depending on the type of workload the CPU is experiencing. Of course, the single cache can help resolve a lot of technical issues with the implementation of this initiative.

The second significant advantage of shared L2 cache memory is that it reduces the workload on the system memory and the processor bus tremendously. In this case the system doesn’t have to control and ensure coherency of the cache memory of different cores. If the system features a dual-core CPU with different caches for each of the cores and both cores work with the same data at a certain time, then this data will be duplicated in both caches. This way it is important to make sure that both caches have the latest data. Before the data is extracted from L2 cache for further processing, each processor core should make sure that the data hasn’t been modified by the second core. And if the data has been modified, then the cache memory needs to be updated immediately. In NetBurst based systems this update is performed via the system bus and system memory. By having a shred cache for both cores you can forget about this inconvenient algorithm once and for all.

Moreover, the CPUs with Core microarchitecture will have special controlling core logic that will allow exchanging data between the L1 caches of each processor core through the shared L2 cache. As a result, the cores will work more efficiently together on the same task.