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Dual-Core Architecture from VIA

The hunt for dual-core architecture carried away not only the leading processor developers. VIA Company, which offers niche solutions for inexpensive and economical systems decided to follow in the footsteps of Intel and AMD and announced their plans regarding the introduction of their dual-core solution in mid 2005. Although we have to point out right away that VIA’s approach to dual-core processor architecture designs is completely different from what the industry leaders have offered.

In fact, the positioning of the upcoming dual-core solution from VIA is also different. While Intel and AMD will offer their dual-core CPUs as high-performance server, desktop and mobile solutions, VIA is going to target these processors for the low-cost small servers or even compact clusters.

The upcoming dual-core processor from VIA will not be built on a single silicon die with two processor cores. The company engineers will try to combine two semiconductor dies with processor cores within a single processor package. This way it will not be a dual-core solution in the full meaning of this word. In fact, they will simply design a dual-processor system in a single package.

Nevertheless, this can turn out a very interesting solution for its market. Especially taking into account that VIA’s dual-core processors will be based on a prospective Esther cores due to be released in May 2005. These 32bit CPU cores will be produced by IBM with 90nm technological process and will boast very low power consumption. The working frequency of the first Esther processors will be about 2GHz while the maximum heat dissipation will be only 15W. Esther CPUs will also support VIA’s brand name PadLock technology accelerating the hardware RSA encoding and NX-bit.

As for the formal features of the upcoming VIA core, we can say that Esther will have 128KB L2 cache, which will make its die only big. The CPUs will use 800MHz Quad Pumped Bus and should theoretically be compatible with Pentium 4 infrastructure. Also VIA is planning to make their Esther support SSE2 and SSE3 SIMD instructions.

Note that the performance of VIA’s upcoming Esther processors will be quite low: this 2GHz core will be able to compete successfully only with Celeron 1.2GHz, which once again determines the specific application field for this type of solutions and dual-core CPUs based around Esther architecture.

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