The first dual-core AMD processors will be manufactured with second generation 90nm production technology, i.e. with SOI and Dual Stress Liner technologies involved. Note that at this stage the cores will not actually undergo any dramatic architectural changes compared with what we have now. It means that most of the features of the first dual-core AMD processors will be identical to those of the currently available CPUs with AMD64 architecture. In particular, these dual-core processors will use 1GHz HyperTransport bus to connect to the chipset and will feature two memory channels to work with DDR SDRAM. However, only due to the absence of radical innovations on the interface level, the upcoming dual-core processors from AMD will be compatible with the regular platforms supporting current single-core Athlon 64 and Opteron solutions.
In fact the only thing that the old platform may require in order to fully support new dual-core processors, is the BIOS update. Since all the logic ensuring successful interaction of the processor cores is inside the CPU, these dual-core solutions can actually work with any chipset.
However, the upcoming dual-core solutions from AMD will still boast a few interesting innovations. First of all, these processors will support 10 new SSE3 instructions, which have been supported by Intel Pentium 4 since the launch of Prescott processor core. Here I would like to stress that this list of SSE3 instructions will not include MONITOR and MWAIT commands supported by the Pentium 4 Prescott, because they serve to manage Hyper-Threading technology, as well as LDDQU command, which was introduced in AMD’s 3DNow! Instructions set long time ago. Secondly, the first dual-core AMD processors will have 4 write combining buffers instead of 2. And thirdly, AMD is going to introduce additional power saving technologies for dual-core processors.
AMD is going to announce its first dual-core processors in mid 2005. They will be launched within the Opteron processor family. In other words, AMD’s strategy implies that they will first introduce dual-core solutions in the server and workstation markets. These are exactly the fields where dual-core processor architecture should be most welcome in the nearest future, according to AMD. First dual-core Opteron CPUs will be compatible with Socket 940 systems, and the total amount of their L2 cache memory will reach 2MB (1MB for each core).
Manufactured with 90nm technology, these CPUs will consist of about 205 million transistors, however, the die size of the semiconductor silicon with two cores will not get any bigger compared to the 130nm SledgeHammer core currently used in AMD Opteron processors. Note that the today’s Opteron CPUs include 105.9 million transistors. Which means that despite the shared resources, the new dual-core architecture will turn out 93-94% more complex compared with a single-core one.
There is another piece of evidence that AMD sticks to the initial plan in terms of dual-core architecture development. The first dual-core Opteron CPUs have already been showcased to the general public. In the end of August AMD showed a four-socket HP ProLiant DL585 server with four dual-core Opteron CPUs manufactured with 90nm technological process. After the corresponding BIOS update this system designed for four Socket 940 processors managed not only to recognize the new processors, but worked with them as a fully-fledged 8-way system.