The year 2005 marked the beginning of use of dual-core processors in desktop computers. On the single silicon wafer of such a processor two normal processor cores are located with all their resources, including L1 cache. L2 cache memory may be independent for each core or shared between them. A memory bus controller, inter-core communication controller, crossbar switch, etc. can also be located on the same wafer. Numerous tests prove the advantages of dual-core processors over single-core ones in a number of applications that support multi-threading. But there seem to have been no tests to show at what speed the cores can exchange data.
How Processors Communicate in Multiprocessor Systems
To better understand what this review is all about, you should be aware of the problems arising in communication between processors of a multiprocessor system.
The processors are working with data that are read from system memory to be modified and then written back. Data are cached in the CPU for faster processing, but more than one processor may request the same data in a multiprocessor system. This is not a problem if both the processors are just reading data, because they are both provided the most recent valid copy from system RAM. But if one of the processors modifies the data, the data are first changed in the cache memory and it is only after a while that they are written into system RAM. So, there is a potential conflict when one processor is trying to read data that have been modified and are currently stored in another processor’s cache.
Methods to solve conflicts of this kind are referred to as protocols of cache coherency maintenance. There exist multiple varieties of such protocols, but describing them is beyond the reach of this review (you can refer to documentation available on the CPU manufacturers’ websites for details).
All the different protocols of maintaining cache coherency usually transfer modified data between the processors via system memory, but the cores of a dual-core processor are located on the same wafer right next to each other, so there’s an opportunity for a direct transfer of data from one core’s cache into another’s. Such transfers might go at a very fast rate. Some PC reviewers even suppose that the total effective capacity of the caches of two separate cores can be compared to a single common cache of the same capacity. Is this supposition true? We are going to give our answer to this question in this review.