Intel Pentium D

The first processor from Intel in this review is Pentium D 920 on the Presler core. The processor has a clock rate of 2800MHz and has two cores with 2MB of L2 cache in each. Unlike the cores of the Athlon 64 X2 which are connected to a single crossbar switch all requests to the system and memory buses pass through, the cores of the Pentium D are connected to the common FSB in a simpler way, via a shared bus interface. So after I’ve examined the speed of data transfers between the cores of the Athlon 64 X2, I do not expect high speed from the Pentium D. But let’s look at the results:

Pic.12: Intel Pentium D. Sequential reading of non-modified data
loaded into the cache of the other core.

Pic.13: Intel Pentium D. Random reading of non-modified data
loaded into the cache of the other core.

Pic.14: Intel Pentium D. Sequential reading of the data
modified in the cache of the other core.

Pic.15: Intel Pentium D. Random reading of the data
modified in the cache of the other core.

The graphs have something in common with the graphs of the Athlon 64 X2, but there are some micro-architectural differences. The Athlon’s step-like manner of random memory access has changed into a wave-like one (Picture 13, 15). The wave is 18 cycles long which is exactly the length of the replay loop CPUs with the NetBurst architecture use to restart a chain of commands in case of cache misses or errors of speculative execution.

At sequential access to the modified data, there’s a considerable and identical increase of latency for each data block the size of 2MB and smaller. To be exact, it is the read speed that’s lower, whereas the speed of reading the 4MB data block doesn’t drop that much. When the data are accessed at random, it is all exactly the opposite – the latency of access to the modified data is lower! It looks like the modified data copied from the first core to system RAM can be transferred by the memory controller into the second core out of the intermediary buffers the same time they are written into the memory chips. This helps save some cycles at random reading. At sequential access, the speed of data transfers into the second core is still limited by the speed of the first core’s writing them into memory because writing data into system RAM takes more time than reading.