Now let’s check out if the data are actually read from system RAM. I’ll measure the speed of data reads from system RAM as I did with the Athlon 64 X2.

Pic.16: Intel Pentium D. Sequential reading of the data from system RAM.

Pic.17: Intel Pentium D. Random reading of the data from the system RAM.

The results aren’t too obvious. On one hand, the latency is higher with 64MB and smaller blocks in comparison with the graphs of reading the unmodified data loaded into the first core (Picture 12, 13). The latency for 8KB and 16KB data blocks have grown the most which corresponds to the size of the L1 data cache of this Pentium D processor. But on the other hand, the latency of reading small blocks has grown in the sequential read graphs (Picture 16) which wouldn’t be the case if the data is transferred directly from one core to another. The read latency for 128KB and larger data blocks almost coincide which means the data are read from system RAM rather than from the another core’s cache. The increase of latency that we observe here may be due to hardware prefetch or to the test algorithm (for example, the data-transfer overhead, which had been previously masked by the operation of the first core, is bigger relative to the real latency).