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Memory of the Future

X-bit labs: Intel once said that the SCC packs an energy efficient DDR3 quad-channel memory controller. Can you provide any additional information about this? What is the difference between this memory controller and those used today?

Sebastian Steibl: The memory controllers are optimized for different operating points. One memory controller has to serve twelve cores, which is quite a high number in terms of parallelism. Hence, the memory controllers are optimized to better serve many single threads rather than serving smaller number of multi threads. The memory controller is optimized for more parallel accesses, whereas traditional memory controllers are more optimized for performance in limited amount of threads.  

X-bit labs: So, that is the memory controller of the future?

Sebastian Steibl: It is the memory controller suitable for many-core architecture. [It also has] a good reason for “large” cores as well.

X-bit labs: What was the response from the software development community on the SCC? Have you already shipped those systems to software makers?

Sebastian Steibl: We have started to share [SCC-based systems] with a very select external partners. There are some interesting results coming out and I guess pretty interesting news are incoming over summer. Those parties have to comment on their work [which has been done].

Time Will Tell

There is a million ways to increase performance of computing. One is to implement larger general processors, another is to incorporate many cores into a chip, yet another is to produce a many-core heterogeneous solution. But there is a problem: the actual software should be ready for the hardware. Within the SCC framework, Intel, at least partly, gives a solution of a problem. What happens next? Only time will tell.

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