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VIA Nano

Having launched processors with x86 microarchitecture for ultra-portable devices, Intel will have to compete not against their eternal rival, AMD, but against VIA that occupied this market niche a few years ago after successful acquisition of “second-tier” processor developers – Cytrix and Centaur. The latest VIA’s solution that has every chance to become a worthy rival to Intel Atom is Nano processor, the first representative of the new Isaiah microarchitecture developed by Centaur technology engineers from scratch.

Although VIA formally positions Nano processor as a continuation to their C7 family and is even pin-compatible with it, this processor is based on a completely new microarchitecture. Nano is VIA’s first processor with out-of-order instructions execution, which Intel has given up in their Atom CPUs for the sake of better energy-efficiency. Nevertheless, although Nano does have all the features of contemporary x86 processors, such as branch prediction algorithms and speculative instructions execution, its TDP lies within the standards for nettops, netbooks and even ultra-portable Internet terminals.

The other side to this relatively complex microarchitecture is higher typical heat dissipation than that of Atom. VIA Nano will have to work at less than 1GHz frequency in order to dissipate 4W of heat like Atom 230. However, even a CPU with out-of-order execution will not be running fast enough at this frequency. Therefore, VIA is offering nettop processors with much higher TDP than that of Intel’s solution: 8W, 17W and even 25W. In other words, it is impossible to directly compare VIA Nano and Intel Atom: these are processors from different “weight categories”.

In this respect, it is not surprising that Isaiah microarchitecture is more similar to Core than to Atom. However, the number of decoders and execution units still make Isaiah inferior to Core. Nano processors can execute three instructions per clock cycle and have 7 execution units: two integer units, two units for SSE and FP operations and three units for work with memory. Here I would like to specifically point out that the implementation of their floating-point units is much more efficient: they can perform widely spread addition and multiplication operations within fewer clock cycles than Intel Core 2 processors. At the same time Isaiah microarchitecture uses a number of contemporary technologies improving processor efficiency even more. For example, Nano processors use analogous macro- and micro-ops fusion approach to instructions decoding and support memory disambiguation technology that allows reordering memory operations.

When VIA engineers launched their new microarchitecture, they made sure that it complied with all contemporary processor requirements. Therefore, Nano became not only the first superscalar VIA CPU with out-of-order instructions execution, but also the company’s first processor supporting 64-bit extensions of x86 architecture. The CPU also has SSE3 instructions set. At the same time, they didn’t forget about a distinguishing feature of all VIA CPUs: additional PadLock unit that provided hardware acceleration of AES encoding/decoding and SHA-1 and SHA-2 cryptographic hashing calculations.

However, Isaiah microarchitecture remained single-core and single-threaded. Nano family doesn’t include any dual-core models and there is nothing in these processors pointing that SMT is even possible. However, VIA doesn’t exclude the possibility of upgrading the microarchitecture later on for the purpose of launching multi-core processors. However, it may only happen when they move to a new manufacturing process.

In the meanwhile VIA Nano is made using not the most advanced 65nm production process. However, it still allows making physically small dies: Nano’s die size is only 63sq.mm. The semiconductor processor die consists of 94 million transistors and is bigger part is given to cache-memory, which is pretty big on Nano. L2 cache is 1MB big, and L1 cache is 128KB split equally between instructions and data. Note that Nano has exclusive cache-memory, i.e. the data stored in L1 cache is not duplicated in L2, which makes the CPU work more efficiently with the memory.

As for the clock frequencies, Nano processor family includes several models working at frequencies from 1.0GHz to 1.8GHz and supporting 800MHz or 533MHz VIA V4 system bus. Nano L processors are targeted for mainstream power-efficient desktop and mobile systems, while U series with lower core voltage is intended for mini form-factor and ultra-mobile systems.

I would like to point out that although Nano looks like a regular desktop processor, VIA engineers paid special attention to its power efficiency. And even though it loses significantly to Intel Atom in typical heat dissipation, the performance-per-watt aspect doesn’t make conclusions so simple any more. Due to unique technological solutions, supported wide range of power-saving modes and voltage regulation depending on the core temperature Nano belongs to power-efficient processor category. It is important to keep in mind here that once VIA switches to 45nm production process in H2 2009 the heat dissipation and power consumption rates of its processors will inevitably improve.

 
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