Memory Controller Supporting DDR2 SDRAM
One of the key innovations, which appeared in the new i925/i915 chipsets is the support of the new DDR2 SDRAM memory. This allows Intel to increase the bandwidth of the memory subsystem. For example the bandwidth of the dual-channel memory subsystem where DDR2-533 SDRAM is used makes 8.5GB/sec, which is 33% higher than the bandwidth provided by the previous generation DDR400 SDRAM. However, I cannot say that the previous platforms based on i875/i865 chipsets had insufficient memory bandwidth. The bandwidth of the dual-channel DDR2-533 memory today is higher than that of the bus between the chipset North Bridge and the processor, which at least means that the CPU will not be able to use the bandwidth of the new memory subsystem to the full extent. However, in case of the integrated graphics core, which also uses quite a bit of the memory subsystem bandwidth, the DDR2-533 can be just the right thing. Besides, you should also take into account that the support of DDR2 memory in the i915/i925 platforms is a good “reserve” for the future. In Q3 2004 already Intel Company will please us with the new CPUs featuring 1066MHz bus, which will be bale to use the bandwidth of the DDR2-533 SDRAM in full.
In order to better understand all highs and lows of the DDR2-533 SDRAM compared with the ordinary DDR SDRAM, you should have at least some idea about the new memory architecture. First of all, note that DDR2 SDRAM is hardly that much different from the regular DDR SDRAM at all. However, while DDR SDRAM transfers two data batches per clock along the memory bus, DDR2 SDRAM effects four data transfers like that. At the same time DDR2 memory is built from the same memory cells as DDR SDRAM , and the performance is doubled due to the use of multiplexing technique.
The memory chips core itself works at the same clock frequency as in case of DDR memory and SDR SDRAM. It is only the input buffers frequency that gets higher, and the bus between the memory core and these buffers that gets wider. The input/output buffers perform multiplexing. The data transferred from the memory cells along the wide bus are actually leaving the cells along the bus of the regular bandwidth but at twice the frequency of DDR SDRAM. This simple approach allows increasing the memory bandwidth even higher without speeding up the memory cells at all. In other words, the memory cells of the today’s most advanced DDR2-533 SDRAM work with the same frequency as the memory cells of DDR266 SDRAM or PC133 SDRAM.
However, this simple way of increasing the memory bandwidth is not free from a few negative consequences of course. First of all, this is higher latency. Of course, the latency is determined neither by the buffers working frequency nor by the width of the bus the data from the memory cells is transferred along. The No.1 factor affecting the latency is the actual latency of the memory cells themselves. This way the latency of DDR2-533 is comparable with that of DDR266 or PC133 SDRAM, and evidently yields to the latency of the most advanced DDR SDRAM working at 400MHz frequency.