The examples are right at hand: the table below lists all latencies and bandwidth for the most widely spread memory standards:
Bandwidth in the dual-channel mode
As we see, if the introduction of DDR2 SDRAM provides a significant advantage in terms of memory bus bandwidth compared with the regular DDR SDRAM, then the low latency is definitely not one of its trumps. In fact, we will hardly see DDR2 memory modules with the latency comparable with that of the DDR400 SDRAM in the nearest future. The modern and fast DDR2-533 SDRAM with 4-4-4-12 timings boasts 1.5 times worse latency than DDR SDRAM working with 2-3-2-6 timings.
Does it make any sense to shift to DDR2 SDRAM at all then? The answer to this question is yes. However, it makes sense only for the Pentium 4 platform, because the performance of this platform really depends on the memory bandwidth a lot. As for Athlon64, for instance, it values lower latencies much more than higher bandwidth that is why AMD’s architecture will hardly benefit from the transition to DDR2 available so far. This is actually one of the reasons why AMD is not going to modify the memory controller of its CPUs to support DDR2 memory in the near future.
In fact, this intention to move to DDR2 SDRAM reminds us of Intel’s attempts to transfer its platforms to RDRAM. However, in our today’s case Intel made sure that its new platforms are backward compatible with the DDR400 SDRAM and that the industry supports DDR2 standard: it is an open standard and the production costs of DDR2 memory modules are as high as those of the regular DDR SDRAM, because they are using the same memory cells, as I have already told you. This way, DDR2 SDRAM will eventually settle down in the fastest Pentium 4 platforms and Intel will hardly have any causes for concern as far as the implementation of this new initiative goes.
Besides the increased input/output buffers working frequency and the use of twice as high multiplexing coefficient, DDR2 also has a few other distinguishing features, which are actually of no key importance. Therefore, we will simply list them in the table below for your convenience and then comment briefly:
Data transfer rate
200, 266, 333, 400MHz
400, 533, (667, 800) MHz
TSOP and FBGA
64Mbit – 1Gbit
256Mbit – 4Gbit
4 and 8
Prefetch (MIN Write Burst)
CAS Latency (CL)
2, 2.5, 3
3, 4, 5
Additive Latency (AL)
0, 1, 2, 3, 4
Read latency - 1
Off-Chip Driver (OCD) Calibration
Bidirectional Strobe (single ended)
Bidirectional Strobe (single ended or
On-die bus termination
2, 4, 8
In fact, I have to specifically stress the Additive Latency mechanism and the bus termination feature built into the chips. The Additive Latency mechanism makes data transfer rate somewhat more efficient. This algorithm solves an occasional problem of DDR SDRAM, when the read commands from one initialized memory bank and the initialization of the other memory bank cannot be performed simultaneously. However, this innovation doesn’t affect the real performance that much.