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Integrated Memory Controller

Nehalem is Intel’s first microarchitecture that has an integrated memory controller inside the CPU. It may see that Intel engineers borrowed this idea from their AMD colleagues, who have been integrating memory controllers inside their processors from 2003. However, it is not quite correct, because the first processors with the integrated memory controller should have been Intel Timna that never saw the light of day but were developed back in 1999. Moreover, no accusations of plagiarism should actually take place, because the memory controller Intel developed for their Nehalem CPUs is very different from the one used in existing AMD processors. Intel’s approach turned out much more massive.

The main feature of Nehalem processors memory controller is its flexibility. Keeping in mind the modular design of the entire upcoming processor family, that may include solutions differing dramatically in features and market positioning, Intel foresaw the opportunity not just to enable or disable buffered modules, but also to vary the memory speed and the number of channels.

The first processors with Nehalem microarchitecture will be quad-core models and they will have a triple-channel memory controller supporting DDR3 SDRAM. This way, desktop systems built on new CPUs will boast unprecedented memory subsystem bandwidth. With three DDR3-1067 SDRAM modules it will reach 25.6GB/s.

However, the main advantage of transferring the DRAM controller into the CPU is not the bandwidth increase, but lowering of the memory subsystem latency. Although Intel designed their new processors to work with DDR3 SDRAM that has relatively high latency, it will still be lower that the latency of Core 2 based systems equipped with DDR2 SDRAM.

To prove that this statement is correct we would like to offer you the results of our memory subsystem tests performed on a Nehalem based platform in Everest 4.60:

Even in single-channel mode, Nehalem memory controller performs better than chipset memory controller in LGA775 platforms. It is an absolutely logical result, because there are no intermediate devices between the CPU and the memory in the new generation processors. However, before that the chipset North Bridge was responsible for work with the memory subsystem and since it had to synchronize the memory bus and the FSB, it did affect the memory subsystem latency.

Another indirect advantage of the built-in memory controller is its complete independence of the chipset and the mainboard. As a result, Nehalem will work with the memory subsystem equally fast in platforms from different developers.

 
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