There is one topic which we haven’t yet discussed. Of course, there was no “cruel intention” behind this, we simply didn’t get a chance to talk about it. However, we cannot completely omit this important matter, so let’s say a few words about it now. This Appendix will be devoted to the processor events and events counters.
Events are actually everything that happens inside the CPU. The micro-operation was sent for execution to fast ALU – this is an event. The data has been requested from L2 cache – this is an event, too. The operands for the micro-operation sent to the FPU have arrived – this is also an event. The data is absent in the L1 data cache – is certainly an event.
So, whenever any of the processor units does something this counts as an event. Of course, among them are events of different importance and priority. Namely, the absence of the data in L1 data cache implies a succession of interconnected actions: L1 cache miss signal is generated, L2 data request is sent, the micro-operation missing the data will be processed in a specific way, the next micro-operation will be sent to he execution units in the meanwhile (if there is an independent micro-operation that has everything necessary for correct execution).
So, if there were a beautiful way to register all important events, we could get very detailed information about what’s actually happening inside the processor.
The processor designers have actually been thinking about it for a long time, too. The information about the processor units functioning is crucially important. True, how can we debug and polish off the branch prediction algorithms if we have no idea how many times the processor made an incorrect prediction and what type of predictions turned out the most difficult? How do we find out if the processor needs a larger cache if we don’t know the cache miss statistics? Does the CPU have enough execution units? Or maybe we could do with fewer execution units, because most of them are idling anyway?
In fact, the processors from different manufacturers (AMD, Intel) have had this special counter system for quite a long time. And its major task is to monitor all major events inside the processor.
The number of these counters is surprisingly big: there are a few hundreds of them! In fact, this number doesn’t seem impressive any more if we think how many events we should actually monitor to ensure proper functioning of the processor. Or if we decide to check the status of all major processor units at a given moment of time. In other words, we need to have at our disposal a huge number of parameters, if we are undertaking some serious investigation here. And all these parameters are monitored by counters.