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ASUS SK8N + AMD Opteron 144: Uniprocessor Workstation on AMD Opteron and NVIDIA nForce3 Professional (page 2)

Category: CPU

by Ilya Gavrichenkov

[ 07/21/2003 | 05:53 PM ]

Closer Look: AMD Opteron 1XX Processor

To tell the truth, I don’t think we need to talk a lot about Opteron processors of the one-way 1XX family. These CPUs have no principal differences from their dual-processor fellows. That is why if you would like to learn more about Opteron architecture and AMD64 technology (which is also known as x86-64), go and check our article called A Glance at the Future: AMD Hammer Processors and x86-64 Technology. On my part, I would like to remind you briefly of the main differences between the new Opteron processor and the widely spread Athlon XP.

Opteron architecture is generally based on Athlon architecture. The major difference between Opteron and the predecessors is the support of AMD64 technology, which allows performing 64bit code while retaining full hardware compatibility with the today’s applications. Actually, that is why the new processors are called eighth generation processors. The implementation of 64bit modes in the new Opteron CPUs caused not only the enlargement of the address space, but also doubling of the general purpose registers with the corresponding growth of their width up to 64bit. However, you will be able to take real advantage of all benefits of 64bit modes only if there is appropriate software supporting AMD64 architecture. However, if you use traditional software in an Opteron system, these innovations will not be involved at all and you will see no effect.

Note that the support of AMD64 technology started expanding into the server field very rapidly. There are at least several Linux clones for Opteron processors and some other server software available today. As for the use of Opteron processors in workstations, the situation here is a little more complicated. In fact, no workstation software has been optimized for AMD64 architecture yet. There is even no operation system from Microsoft supporting 64bit mode of Opteron processors. However, the situation is not completely hopeless. For example, the NUMA memory architecture (Non-Uniform Memory Access), used in multi-Opteron systems, is already supported in Windows 2003 Server.

This way, Opteron processors are most likely to work in their regular 32bit mode in top graphics workstations. However, even in this case the new AMD Opteron CPUs can boast a number of enhancements, which will allow them to outperform AMD Athlon XP working at the same core frequency. Among these enhancements we would like to point out the following:

• Memory controller integrated into contemporary Opteron processors supporting dual-channel DDR333 SDRAM;
• Separate Hyper-Transport buses between the CPU and the chipset implementing the AGP 8x support and input/output functions and serving to build up multi-processor configurations;
• Increased 1MB L2 cache featuring higher bandwidth (which might be achieved due to the wider 128bit bus between the cache and the processor core);
• Fully-fledged SSE2 instructions support;
• Longer 12-step integer pipeline and 17-step floating-point pipeline (by Athlon XP these pipelines are 10 and 15 steps long, respectively). This improvement primarily serves better architecture scalability.
• Larger integer scheduler buffers (24 entries against 18 entries by Athlon XP);
• Larger TLB. The TLB of L1 instructions cache has been increased from 24 to 40 entries and the TLB of L2 cache grew up to 512 entries (while Athlon XP has 256 entries);
• Enhanced branch prediction algorithm with the history chart increased up to 1600 entries (Athlon XP has only 400 entries).

As we see, the undertaken architectural changes are quite significant, especially against the background of Athlon XP processor. Moreover, most of these improvements will definitely have a positive effect on the performance of Opteron processors used as a basis for workstations. Here we should first of all stake faster memory subsystem performance together with faster and larger L2 cache, but we shouldn’t also disregard the more in-depth architectural changes. I would like to single out SSE2 instructions support: most today’s 3D rendering applications, such as Lightwave 7.5 are currently optimized for this particular instructions set.