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Intel Pentium M 780 as Heart of Your Desktop PC, with ASUS CT-479 Adapter (page 5)

Category: CPU

by Ilya Gavrichenkov

[ 06/20/2005 | 01:46 PM ]

SSE2 instructions: All Pentium M processors support SSE and SSE2 extensions. So, the number of supported SIMD instructions was extended in Intel’s mobile processors since the Pentium III. Yet, the Pentium M does not support the SSE3 set which first appeared in the Prescott-core Pentium 4.

Power-saving L2 cache: One of the remarkable things about the Pentium M is its very large L2 cache. The size of this cache is 2 megabytes. Using such large amounts of cache memory helps to unload the system bus and the memory bus which ultimately leads to lower power consumption of the CPU. We should also note that the Pentium M uses a special technique for reducing the power consumption of the cache. Like in other processors from Intel, the cache memory of the Pentium M has eight associativity sets. These sets are further divided into four quadrants in the Pentium M, each of which is accessed independently. As a result, Intel managed to considerably reduce the power consumption of the L2 cache (almost in four times). The downside of this solution is that the latency of the L2 cache has increased by 1 cycle if compared with the latency of the L2 cache of Pentium III processors.

As for the L1 cache, it is 64 kilobytes large (32 kilobytes for each code and data). This is two times the size of the Pentium III’s L1 cache. Another point of difference between the cache memories of the Pentium III and Pentium M is that the cache line of the latter is longer, 64 bytes. This change helps to work more efficiently with data structures of modern applications.

SpeedStep III technology: The Pentium M is intended for mobile computers, so it was equipped with additional power-saving technologies, SpeedStep III being the main one. According to available empirical data, the power consumption of processors depends linearly on the frequency and load of the CPU and quadratically on the CPU voltage. The developers have long been considering the idea of reducing the power consumption by reducing the frequency and voltage of the processor when it is not required to work at the full capacity. For example, the CPU load is far from 100% in a majority of office applications which are the most popular applications running on mobile computers. So, the frequency of the CPU can be reduced in such cases without compromising the user’s comfort. Besides the frequency, it is also possible to reduce the CPU voltage, and this is the point of SpeedStep technology.

The first implementation of SpeedStep in Pentium III-M processors offered two CPU modes: performance (or standard) and economical (with a lower frequency and voltage). The computer would enter the economical mode when the battery charge was below a certain level or when the CPU was idle. The second version of SpeedStep, implemented in mobile Pentium 4 models, added a third, adaptive mode. In this mode the switching between the max performance and reduced power consumption modes was performed dynamically, depending on the CPU load. That is, the CPU by default worked in the reduced-consumption mode, but could deliver the maximum performance as soon as a resource-consuming application was launched. The third version of SpeedStep technology, available in the Pentium M, features a more flexible adaptive mode. Pentium M processors have up to seven different states with reduced frequency and voltage each of which can be activated any time depending on the CPU load. Thus, SpeedStep III is a highly flexible technology that helps to reduce greatly the power consumption of the processor without any discomfort for the user.