Articles: CPU
 

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Part 5: Instruction Set and Registers

Here is a picture that illustrates the internal structure of the processor:

There are a few things you can notice in the picture: the processor has two execution pipelines, two FPUs, and a unit for processing SIMD instructions called AltiVec. But there is one thing that catches the eye: the instruction processing stage called “Decode”. But why Decode? We have been taught that RISC means a Computer with a Reduced Instruction Set: simple instructions are ready to be fed directly to the processor. Why the processor transforms them here? Why does it need to make those wonderful RISC instructions into anything else? How does it all work?

It is all logical. PowerPC970 processor does transform RISC instructions into some internal set of instructions (this is quite a mysterious thing and I found no information about it, except the fact that it does exist). PowerPC970 uses an internal instruction set, which is completely different from the external set. This feature makes it look very similar to x86 processors that transform external irregular x86 instructions of variable length into internal commands (or command sequences) of constant length. We got used to seeing that in x86 processors, but it is quite strange to see this in a RISC one. A set of simple and short instructions have always been considered the key advantage of the RISC architecture. Thanks to that simplicity, the execution units were relatively simple, and many commands were executed directly, without any transformation or translation. But it is one thing when you have to execute directly a few dozen instructions, and it is quite another, when the number of supported instructions approaches two hundreds (this processor supports the AltiVec set that consists of as many as 162 instructions). So, I think this measure was adequate: it is easier to add a decoding unit into the processor rather than to try executing several hundred instructions directly.

The problem is even not about the AltiVec set, but rather about IBM (with its clients) having accumulated a lot of software, which is too expensive to be just thrown away. The older instruction set doesn’t support modern programming, and the standard methods for increasing the processor performance are practically exhausted. So, similar problems (the need to keep the money invested into older software together with the need for higher performance) met similar solutions for the Mac and for the x86: introduction of the decoding unit.

History once again shows its ironic nature. The instruction set for the x86 and the system of decoders (often referred to as “crutches for the x86”) have always been the laughing stock for the proponents of the RISC architecture. In fact, the translation of x86 instructions into RISC-like commands inside the processor was considered a victory of the RISC camp. They used to say that a real processor didn’t need to transform instructions into a “digestible” form, while “crippled” x86 processors had to translate their external instruction set into the “right” RISC-like internal set. I wonder what they are going to say now. :)

 
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