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Part 3: Introducing the PowerPC970

Let’s be back to the platform. Next goes the microprocessor, the brain of each computer. So, what innovations did the current IBM PowerPC970 processor bring to the user compared to its chronological predecessor, the Motorola G4+? By the way, note that the main supplier of processors for Apple has changed – this is a rare thing in the business world. How good is this chip? How does it rank among the newest representatives of the x86 architecture?

The basic characteristics like die size, frequency and heat dissipation come first. The following table compares the PowerPC970 to other modern processors:

 

Process

Die Size

 Transistors

Core Voltage

Power Dissipation

PowerPC 970 1.8GHz

0.13um SOI

118 mm2

52 million

1.3V

42 Watts

Pentium 4 2.8GHz

0.13um

131 mm2

55 million

1.525V

68.4 Watts

Opteron 144 1.8GHz

0.13um SOI

193 mm2

106 million

1.5V

up to 89 Watts*

G4e 1GHz

0.18um

106 mm2

33 million

1.6V

30 Watts

* - This is the maximum heat dissipation for the entire platform for today. I couldn’t find the heat dissipation specs for the processor alone. Some sources say the Opteron 144 1.8GHz has a maximum heat dissipation of 70W.

It is clear the PowerPC970 is much closer to the modern x86 processors, than to its predecessor, and even surpasses them in some aspects like heat dissipation. The excellent value of this parameter is partially due to the lower operational voltage (IBM owns one of the best technological bases in the industry overall).

The following table shows you the number and organization of caches in the processors:

 

L1 I-cache

L1 D-cache

L2 Cache

PowerPC 970 1.8GHz

64KB, direct mapped (!)

32KB, 2-way assoc.

512KB, 8-way assoc.

Pentium 4 2.8GHz

12K uops*

8KB, 4-way assoc.

512KB, 8-way assoc.

Opteron 144 1.8GHz

64KB, 2-way assoc.

64KB, 2-way assoc.

1024KB, 16-way assoc.

G4e 1GHz

32KB, 8-way assoc.

32KB, 8-way assoc.

256KB, 8-way assoc.

* - As you know, Intel doesn’t publish the size of the Trace cache in kilobytes. Making assumptions about the size of a micro-op (micro-architecture op-code) helps to estimate roughly the size of this cache at 80KB-120KB! On the other hand, fewer instructions can be stored in a cache of this size, since the Trace cache contains them in the decoded form in which instructions tend to “swell up”. I guess this is the reason for Intel to forget that a cache can be measured in kilobytes rather than in micro-ops. Or maybe they just try to be correct and not to confuse apples with oranges. Whatever the case, we can very roughly tell the capacity of this cache basing on the following fact: the average size of an x86 instruction is 3-4 bytes. Let’s take it to be 4 bytes. Most of x86 instructions are decoded into two micro-ops. That is, 12,000 micro-ops correspond to about 6,000 x86 instructions. That’s how many of them (in the standard form) fit into the 24KB data cache. Once again, this estimate is very rough. Anyway, I think this is the upper estimate for the size of the Trace cache – it can’t possibly be any bigger.

 
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