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I also have to say that besides the above mentioned innovations, the transition to 90nm production process also brought a number of less radical changes. In particular, Intel started using new Low-k CDO dielectric to isolate copper interconnects. Moreover, 90nm semiconductor dies now have more metal (copper) layers: Prescott has 7 of them, while Northwood processors had only 6. This innovation provides higher flexibility during complex semiconductor devices designing and allows fitting more transistors into a smaller die. In fact there is nothing revolutionary about it: AMD Athlon 64 processors, for instance, feature 9 copper metal layers.

I would like to draw your attention to the fact that Intel managed to perform the transition to a new production technology at the least expense possible. New lithographic equipment with 193nm wave length is used only for critical spots of 90nm dies. In all other cases Intel does very well with the old 248nm lithography. This is exactly the reason why Intel replaced only 25% of equipment on the fabs producing 90nm dies. However, I should stress that we can hardly consider the use of phase masks (required by 248nm lithography) a successful solution today. Nevertheless, Intel is going to reequip its facilities completely only when they shift to 65nm production process.

Prescott Core

Prescott core is completely different from the previous processor dies used in Pentium 4 CPUs. It would be absolutely incorrect to claim that the new Prescott is none other than the same Northwood core featuring larger cache-memory and manufactured with finer technology process. The differences between the newcomer and the predecessor are much more essential. In fact, the example is right here: look at the photo of the Prescott processor core:

When they worked on Prescott many of the internal functional units were developed anew. Besides, the engineers resorted to automated design a lot. As a result, Prescott core looks very much different from all other dies. Unfortunately, we can’t clearly single out separate functional units on the picture above. Many processor parts appeared simply “spread over” the entire die. The thing is that at the development stage they optimized the Prescott core layout so that to ensure high clock frequency potential and even heat dissipation all over the die. As a result, overheating of separate functional units will not be as typical of the Prescott core as it is of any other processor die. This way, we can state that Intel gave up the old processor development algorithm, when all the processor functional units were developed separately and then put together into the same die.

As for the basic features of the Prescott core, they are given in the table below, compared with the predecessors from Intel and competing solutions from AMD:

 

Intel Pentium 4

Intel Pentium 4

Intel Pentium 4 Extreme Edition

AMD Athlon 64

AMD Athlon 64 FX

AMD Athlon XP

Processor core

Prescott

Northwood

Gallatin

ClawHammer

SledgeHammer

Barton

Socket

Socket 478

Socket 478

Socket 478

Socket 754

Socket 940

Socket A

Frequencies

2.8-3.4GHz

1.6-3.4GHz

3.2-3.4GHz

2.0-2.2GHz

2.2GHz

Below 2.2GHz

Production technology

0.09 micron, «strained» silicon

0.13 micron

0.13 micron

0.13 micron, SOI

0.13 micron, SOI

0.13 micron

Number of transistors

125mln.

55mln.

178mln.

105.9mln.

105.9mln.

54.3mln.

Die size

112 sq.mm

131 sq.mm

237 sq.mm

193 sq.mm

193 sq.mm

101 sq.mm

L1 data cache

16KB

8KB

8KB

64KB

64KB

64KB

L1 instructions cache

12000 uops

12000 uops

12000 uops

64KB

64KB

64KB

L2 cache

1024KB

512KB

512KB

1024/512KB

1024KB

512KB

L3 cache

-

-

2MB

-

-

-

SIMD instructions

SSE3/ SSE2/ SSE

SSE2/ SSE

SSE2/ SSE

SSE2/ SSE/ 3DNow!

SSE2/ SSE/ 3DNow!

SSE/ 3DNow!

x86-64 support

-

-

-

+

+

-

Integrated memory controller

-

-

-

Single-channel DDR SDRAM

Dual-channel DDR SDRAM

-

As we see, Prescott has more than twice as many transistors as Northwood. However, it is not because of the twice as big L2 cache, because l2 cache of the Prescott processor occupies only 25% of the die size. Also this number of transistors is very unlikely to be required for larger L1 data cache or support of 13 SSE3 instructions. It looks as if there were other important reasons for these extra transistors to appear in the new Prescott die. Let’s try to find out what they are.

 
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