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Articles: CPU
Replay: Unknown Features of the NetBurst Core (page 9)Category: CPU by Victor Kartunov , Yury Malich , Jan Keruchenko aka C@t , and Vadim Levchenko aka VLev [ 06/06/2005 | 04:20 PM ] STLF ViolationsThose of you who have studied NetBurst micro-architecture carefully should know that Store operation is split into two quasi-independent micro-operations: Store data (STD) and Store Address (STA). The results of these two micro-operations are combined in the Store Buffer (SB). The data stays in the SB until the record command retires. After that they are saved in the cache and RAM via the intermediate Write Buffer, where the modified data is put back together. Data load commands perform speculative reading of the data which is not in cache yet directly from the SB. This process is called store-to-load-forwarding (STLF). In order to the STLF to end up successfully, certain conditions should be fulfilled:
The violation of any of the above mentioned conditions may lead to very unpleasant delays. The re-execution of data load command, which couldn’t be completed successfully because of the STLF violation is also carried out via the replay system. Well, in order for Store to be able to send the data for Load command, SB should have the STA and STD results ready in advance. Although “IA-32 Intel Architecture Optimization Reference Manual” classifies this condition as “Store Forwarding Restrictions”, we should realize that it requires specific processing and leads to specific consequences. The true STLF violation, when the data already located in the SB cannot be sent, results into a significant delay: store and all preceding instructions should retire first and the store result should be saves in the cache. In our case, i.e. during STLF Restriction on Data Availability, we should only wait for the STA/STD result. As you may have already guessed, replay works here: LD and all dependent instructions are sent to RL and circle there until the Store results arrive. We have just studies two types of STLF violations: when by the time Load should be executed either STA or STD result is not ready yet (the third type, when none of the results is ready will be determined by the worst consequences of the first two types). <%BANNER[banner_468x30]%>
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Category NewsCategory: CPU Thursday, July 17, 20082:36 pm AMD’s Chief Executive Officer Hector Ruiz Steps Down. Dirk Meyer Becomes New Chief Exec of AMD 12:15 pm Intel: Atom Will Not Substitute Celeron Processors. Intel Denies Possibility to Change Celeron for Atom Wednesday, July 16, 200811:55 pm Intel Promises to Ship 100 Million 45nm Microprocessors This Year. Intel Says 45nm Process Technology Ramp Better than Ever 7:06 pm Intel to Launch Another Offence with Nehalem Microprocessors Later This Year. Intel to Aggressively Push Nehalem Micro-Architecture into High-End Desktops Tuesday, July 8, 200811:01 pm DreamWorks and Intel Sign Pact: Larrabee, Xeon Set to Be Used. DreamWorks Switches from AMD to Intel 6:07 pm AMD Loses Microprocessor Revenue Share to Intel – iSuppli. AMD, Intel Continue to Gain CPU Revenue Share All Latest News <%BANNER[right_130x130_1]%>
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