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AMD Trinity Hybrid Series

The AMD Trinity is the second variant of APUs from AMD. The first one, codenamed Llano, was introduced to desktop users as part of the Socket FM1 platform but didn’t really take off. The old microarchitecture and, consequently, low performance of the x86 cores coupled with the short declared lifecycle of the platform itself didn’t help to make it attractive. The new APU is different, with all of the older downsides having been corrected. The CPU part of the Trinity sports the most advanced microarchitecture AMD has at its disposal and the Socket FM2 platform is expected to have a rather lengthy lifecycle.

 

Like AMD’s first-generation APUs, the Trinity incorporates three constituent parts, each of which has been updated. The conventional CPU part is now based on x86 Piledriver cores which are well known to users by AMD’s new Vishera series. The difference is that the Trinity APUs may only have a maximum of four x86 cores. Thus, they have only one pair of dual-core modules which, according to AMD’s design concept, have a whole set of subunits shared by the two cores: cache memory, instruction fetch unit, instruction decoding unit, and a floating-point unit. In other words, the Trinity is at best only one half the top-end AMD FX CPUs in terms of computing performance, yet features all the advantages of the second-generation Bulldozer architecture.

Meanwhile, the 32nm semiconductor die of a Trinity CPU is as large as 246 sq. mm, which is but 22% smaller than that of an 8-core Vishera. Why? Because the larger part of the Trinity die is occupied by an integrated graphics core codenamed Devastator. It introduces into AMD’s integrated solutions the VLIW4 architecture which has come to APUs from Radeon HD 6900 series graphics cards. The change of architecture doesn’t affect the total number of shader processors compared to the previous-generation integrated graphics core but helps make a more efficient use of them, improving the overall computing density. In its maximum version the Devastator has six SIMD engines, each of which includes four texture fetch units and 16 VLIW4 stream processors, and also 24 texture-mapping units and 8 raster operators. Thus, it seems to be about one fourth the Radeon HD 6970 GPU, but with lower clock rates.

 

The third constituent component of the Trinity is the integrated North Bridge responsible for system memory access. The Socket FM2 platform developed by AMD specifically for new-generation APUs supports dual-channel DDR3 SDRAM at frequencies up to DDR3-1866. Since both the CPU and GPU cores use this memory controller, the memory bandwidth becomes a crucial factor. However, to reduce the transistor budget and lower the manufacturing cost, the Trinity is devoid of L3 cache memory which would be most useful in this design.

The Trinity series includes several APU modifications varying not only in clock rates of their x86 and graphics parts but also in the number of CPU cores and GPU stream processors. We’ve managed to collect the entire set for this test session as listed in the following table:

Take note that, although the Trinity uses a graphics core with VLIW4 rather than GCN architecture, AMD markets it as Radeon HD 7000 because the Devastator is compatible with DirectX 11, OpenGL 4.1 and OpenCL 1.1 APIs and features AMD’s latest video engine HD Media Accelerator. Thus, the Trinity provides extensive HD video processing capabilities including hardware decoding of popular formats (UVD3) and hardware encoding into H.264 format (VCE).

Now let’s have a closer look at the APUs we’re going to test.

 
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