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| CPU Naming GuideUpdated - February, 26Aren't you lost among all these Merced, Katmai, Celeron, Mendocino and the like? We are absolutely confused with all these strange names and that's why we decided to classify and bring into a system all the names of x86 processors. And in order to make this system more informative we included the following info for each processor mentioned: family/generation, architecture, CPU clock frequency, system bus frequency, L1 cache size, L2 cache size, manufacturing technology, the launching date, additional instructions if present, physical interface. Anyway, the info you'll find here comes from different sources, some of which may even contradict each other. In this respect all your comments and additions are most welcome. IntelPentium. The first processors of P5 family appeared in the far March 1993. Since the court refused Intel's action against AMD concerning the name, not to repeat the mistake with i486 Intel made up its mind to give a new offspring a name, which later on became a common noun. The first Pentium generation was called P5, also known as 80501, - it was made with 0.80 micron technology, supported 60 and 66MHz FSB frequencies and was designed for 5V vcore. It had the grid array pinout. However, we have to mention that the bus frequency of those processors equaled to that of the core. They were designed exclusively for Socket 4. The next step in this family history was P54, aka 80502, which appeared a year later. It supported 3.3V core voltage and the pins are arranges in staggered rows of a grid array. It was manufactured already with 0.50 and then even with 0.35 micron technology. The processor clock frequency lied within 75-200MHz, and the bus frequency - within 50-66MHz. It had a 16KB L1 cache. By the way, it was the first time they used a separated cache: 8KB for data and 8KB for instructions. Form factor - for Socket 5. IA32 architecture. The instructions set remained unchanged since the times of i386. Pentium w/MMX technology. The next important move was the launching of P55 processor, which was the first CPU with a new set of 57 MMX instructions. The occasion took place on 8 January 1997. The technology kept on developing and those processors were already manufactured with 0.35 micron process. Vcore was changed to 2.8V, which required the corresponding changes of the mainboard construction: namely they needed an additional voltage regulator. L1 cache was made twice as large as it used to be before - 32KB. The processor intended for Socket 7 only worked at 166-233MHz core and 66MHz bus frequency. Well, here the story of the Pentium family for desktop PCs stops. Tillamook. This processor was initially intended for notebooks. Due to the significantly improved 0.25 micron technology the developers managed to increase the CPU clock frequency up to 266MHz and at the same time to reduce core voltage and power. This allowed mobile computers to walk side by side with desktop ones. This processor continues Pentium family and has 32KB L1 cache as well as MMX instructions set. It was available in various versions with the core clock frequencies starting from 133MHz and finishing with 266+MHz, while the bus worked at 60-66MHz. The package type was TCP and MMC (although there are some converters to install Tillamook into Super7 socket). The device came into the world on 8 January 1997. Pentium Pro. It was the first CPU of the 6th generation, a quite revolutionary thing for its time, actually. This processor was the first where Intel dared use L2 cache, which was packed together with the core and worked at the CPU frequency. Its manufacturing cost quite a lot and the situation in this respect has hardly changed since it appeared in the market - 1 November 1995. It was manufactured with both: 0.50 and 0.35 micron technology. The latter allowed increasing the cache size. This CPU was produced with 256, 512, 1024 and 2048KB L2 cache and 16KB L1 cache. The CPU clock varied within 150-200MHz and the bus frequency - 60-66MHz. The processor was made for Socket 8 only. Pentium Pro supported all Pentium instructions (not MMX, of course), as well as some new ones such as cmov, fcomi, etc. This CPU was the first to boast an independent dual bus. Later on Pentium II inherited all this stuff (long before its official launch Klamath1 was considered simply as Pentium Pro with MMX and improved performance in 16bit applications). By and large, it passed ahead of its time... Pentium II. This P6/x86 family representative appeared in May 1997. This name covers the processors intended for different market sectors. Pentium II (Klamath1, Deschutes, Katmai, etc.) - for mass market of the mid-level PCs, Celeron (Covington, Mendocino, Dixon, etc.) - for cheap low-end computers, Xeon (Xeon, Tanner, Cascades, etc.) - for highly efficient servers and workstations. It is available in the following modifications: Slot 1, Slot 2, Socket 370, as well as mobile versions. Now let's take a closer look at each family. Klamath1. It is the first processor of the Pentium II family. It was manufactured with an outdated 0.35 micron technology that's why the processor clock frequencies range is not that impressive: only within 233-300MHz. System bus frequency - 66MHz, and 512KB L2 cache is placed onto the processor board and runs at half the processor frequency. The first models were available with 256KB L2 cache as well as with 512KB. L1 cache is 32KB. Vcore - 2.8V. The device can also boast an MMX block. Besides, it is the first Slot 1 processor (SECC cartridge). It saw the light on 7 May 1997. Deschutes. This processor shows the further development of Pentium II family, namely the use of the improved 0.25 micron technology, 2.0V core voltage. As a result, they managed to increase the core frequency to 266-450+MHz, and the system bus frequency to 66-100MHz. L1 cache is 32KB, 512KB L2 cache is located on the processor board. The processor is designed for Slot 1. It was launched on 26 January 1998. Deschutes is the last core officially used in Pentium II processors. Although the latest Pentium II 350-450 models were built on the core looking more like Katmai with a cut down SSE block, of course. Besides, the processor cartridge turned into SECC2 - the cache was placed on the one side of the core instead of two, the cooler fastening mechanism was changed. Tonga. It is a very interesting fellow. It was the first time we came across this name while writing the current article. The thing is that Intel never focused on the fact that Mobile Pentium II based on 0.25 micron Deschutes core would be called Tonga. However, there is not much to be surprised at, actually, because it is just a codename and into the market all processors get with absolutely different names. Anyway, for the first time it appeared on 2 April 1998. The CPU clock frequency lies between 233 and 300+MHz, the bus frequency is quite standard - 66MHz. It is manufactured as Mini Cartridge Connector and Mobile Module Connector 1 and 2 (MMC-1 and 2). Katmai. It is the direct successor to Deschutes. Among the changes introduced are the added SSE (Streaming SIMD Extensions) block, a slightly enlarged MMX instructions set, improved memory streaming. It is manufactured with 0.25 micron process, works at 450-600MHz clock frequency. 512KB L2 cache memory is located on the processor board. The supported bus frequency is now 100MHz, however, since Coppermine was delayed, 533 and 600MHz models intended for 133MHz system bus were launched only in September. Celeron. This CPU can be called a revolutionary device: Intel has finally paid a bit of its precious attention to the low-cost computers market. Well, it is a family of quite inexpensive processors with or without L2 cache. At present we can name the following members of this family: Covington, Mendocino, Dixon, some of which are still manufactured. The first Celeron was launched in April 1998. It is available as Socket 370 and Slot 1 version. Covington. It is the first processor of the Celeron family. The CPU is based on Deschutes core and was manufactured with 0.25 micron technology. It works at 266-300MHz core frequency and at 66MHz bus, possesses 32KB L1 cache (16KB for data and 16 for instructions) and no L2 cache. It turned up on 15 April 1998. In order to reduce the manufacturing expenses it was made without L2 cache and protection cartridge. Vcore - 2.0V. Physical interface - Slot 1 (SEPP - Single Edge Pin Package). Mendocino. This device continued the Celeron family. Unlike its predecessor, it has on-die 128KB L2 cache memory. The processor clock frequency is 300-533MHz, the bus frequency is 66MHz. The used technology is now 0.25 micron and 0.22 micron for Socket 370 models, which makes them more overclockable. The processor performs pretty nicely due to the cache running at the CPU frequency. The launching took place on 8 August 1998.The core voltage makes 2.0V. At first it appeared in Slot 1 form-factor, then Slot 1 (300A - 433MHz) shared its position with Socket 370 (300A - 533MHz) version, and now we can state that the latter is slowly replacing Slot 1 in the market. Dixon. Well, this is the next chapter in Celeron history. This low-cost processor intended for notebooks is manufactured with 0.25 micron technology. L1 cache is 32KB, and like Mendocino it also has on-die L2 cache. However, unlike its predecessor, Dixon has a larger L2 cache - 256KB. The core frequency lies between 300MHz (Celeron 3090A) and 500MHz, the bus frequency - 66MHz. According to the official classification, it is known as mobile Pentium II. Coppermine. This is a Pentium III made with 0.18 micron technology with 256KB L2 on-chip cache. The frequency is starting from 533MHz and up. Besides FSB133 versions there are also FSB100 versions available (for instance, 667/650MHz). The today's possible maximum is supposed to be about 1GHz, which is expected to be achieved in the second half of the year 2000. It is the last processor made with Slot 1 form factor. Coppermine (FC-PGA 370). This is a cheaper Coppermine in FlipChip PGA 370 form-factor intended for Socket 370 mainboards (although they are incompatible with PPGA form factor used for Celeron Socket370) and 100MHz FSB frequency. FC-PGA Coppermine processors under 600MHz do not support SMP configurations. The lowest CPU clock frequency is 500MHz, then it grows within Coppermine family. Requires 1.65V core voltage. It is sharing the market with Slot 1 processor version during the first half of this year, and after that it is expected to occupy the whole niche and to oust Slot 1 from the market. Coppermine 128K. A new stage in Celeron evolution. Starting from 566MHz, Celeron has to get a new Coppermine core with L2 cache cut down to 128KB. It means that in terms of its features, this processor will be as close to Pentium III based on Coppermine as possible. Besides, it will be the first time Celeron gets SSE support. Its frequency is expected to rise up to 667MHz within the first half of the year 2000. Timna. It's a Coppermine 128K with the integrated on-chip graphics core and SDRAM controller. In other words, it is more likely to be a chipset than a CPU. It is intended for very cheap PCs and playstations. The core clock will supposedly be from 667MHz. The device is planned for September 2000. Xeon. A few years had passed when Intel decided to replace Pentium Pro. Like its predecessor, Xeon can boast L2 cache memory working at the processor frequency. However, in PPro the processor package was the uniting element for cache and core, while in Xeon it is the cartridge. This is the first processor for Slot 2 designed for powerful servers and workstations in the first place. It can also work in multiprocessor configurations. This processor is based on Deschutes core and is manufactured with 0.25 micron technology as well as its own cache. By the way, the cache can be 512, 1024 or 2048KB, which results into high cost and heat emission. Tanner. It is a Pentium III Xeon, i.e. it differs from Xeon as Katmai from Deschutes. This processor is first of all developed for Hi-End servers, and works at 500MHz core and 100MHz bus frequency. As all the other Xeons, it has a 512, 1024 and 2048KB CSRAM L2 cache running at the processor frequency. Of course, we shouldn't forget about 32KB L1 cache, MMX and SSE support. Cascades. Here we see a Pentium III Xeon made with 0.18 micron technology. In fact, it is a server Coppermine. It possesses 256KB L2 on-chip cache, 600MHz core and 133MHz bus frequency. The first versions work only in dual CPU configurations and only at 133MHz FSB frequency. In Q1 they plan to reach 866MHz and in Q1 - to increase L2 cache size up to 2MB. This processor is designed for Slot 2 form factor. Willamette. This is the next principally new IA-32 processor from Intel after Coppermine intended for ordinary PCs. Instead of the old GTL+ it uses a new system bus - Quad Pumped 100MHz with the end frequency of 400MHz. L1 cache is supposed to be 256KB, L2 - under 1MB. Besides, Intel took a number of steps toward performance increase: added execution units and decoders, increased buffer size, etc. As to the today's info, this CPU works almost at the same clock frequency as Coppermine, is close to Coppermine in integer operations and proves about 5 percent faster in floating point operations. Intel will start manufacturing this device with 0.18 micron technology and then shift over to 0.13 micron. The core clock frequency is announced starting from 1GHz and up. The processor is supposed to be introduced in Socket-423 form-factor and is expected to come out in October 2000. Northwood. This is a mobile Willamette. This CPU is supposed to become Intel's test platform on the way to 0.13 micron technology (namely, it is likely to play the same transitional role as Coppermine did during the shift to 0.18 micron). The launch is expected to take place in 2001. Foster. This is a server Willamette. The system bus will supposedly support 400MHz. L1 and L2 caches will be significantly larger. The CPU clock frequency is expected to exceed 1GHz. This device is probably due in the end of 2000 - in the beginning of 2001. And the form-factor will supposedly be a Slot M. It looks as if this processor were the last IA-32 from Intel - a sort of a transition link towards IA-64, using the same bus as McKinley. Merced. This is the first processor with IA-64 architecture, which is hardware compatible with IA-32 one. It will include 2-4MB of three-level cache memory with the 0-level memory. And it will perform almost 3 times as cool as Tanner does. This processor will be manufactured with 0.18 micron technology, and will work at 800MHz core and 266MHz system bus frequency. It will be almost 20 (!!!) times cooler than Pentium Pro in FPU operations. It will be available with Slot M physical interface and of course with MMX and SSE(2) support. The thing is expected to appear in the mid 2000. It will sell as "Itanium". Itanium Under this brand they will sell Merced processor. McKinley. The processor is planned for the first half of 2001, and will represent the second generation of IA-64 architecture processors. It will support starting from 1000MHz core clock frequency. The performance is expected to grow twice as great as by Merced. Besides, the bandwidth of the data bus (with the general frequency of 400MHz) will increase by three times, L2 cache will also get bigger compared to Merced. Again it will be 0.18 micron process, and a year later - 0.13 micron. Also Slot M physical interface. It will use the same i870 chipset as IA32 Foster. Madison. McKinley's successor, which is going to come out in 2002. In other words, it will be the old McKinley but built with a new copper 0.13 micron technology. Deerfield. This processor is expected only in 2003. It will be manufactured with a new copper 0.13 micron technology by Motorola and will succeed Foster. As all the other new CPUs, it will be designed for Slot M. It is positioned as a low-cost processor for IA-64 workstations and mid-level servers. AMDK5. It was AMD's first processor, which was designed to compete with Intel Pentium. It supports Socket 5. Like Cyrix 6x86, AMD used PR-rating from 75 to 166MHz, while the system bus frequency was 50-66MHz. The processor had 24KB L1 cache (8KB for data and 16KB for instructions). As for L2 cache, it was installed on the mainboard and worked at the system bus frequency. There were 4 versions of this CPU - K5-7, 90, 100 (PR-rating corresponded to the processor frequency, it was manufactured with 0.6 micron technology). Namely, they were: K5-100 (0.35 micron), K5-PR120, PR133 (PR-rating corresponded to 90 and 100MHz, manufactured with 0.35 micron technology, enhanced core), and K5-PR166 (real frequency equaled 66MHz x 1.75) with an unusual multiplier. K6. AMD started shipping this processor in April 1997 (Model 6), a month before Pentium II was launched. The device was made with 0.35 micron technology (later on 233MHz K6 processors were manufactured with 0.25 micron). Its working frequency varied from 166 to 233MHz (note that the 233MHz version - the officially overclocked one - required 3.2/3.3V instead of the usual 2.9/3.3V). it was based on the 686 processor design developed by NexGen bought by AMD. Compared to its predecessor this CPU got a MMX module, increased L1 cache - up to 64KB (32KB for instructions and 32KB for data), and the higher core clock frequency allowed AMD to give up PR-rating. K6 suggested the solutions to achieve higher performance when working at the same frequency, namely they were speculative execution and internal RICS-like architecture. All the other AMD processors inherited this feature. Some time later they started supplying K6 Model 7 (mobile version) working at 266 and 300MHz processor and 66MHz FSB frequency and manufactured with 0.25 micron technology. K6-2. This device represents the next K6 generation. It came out in May 1998. The main differences between this processor and its predecessor are the supported additional instructions set - 3DNow! and 100MHz FSB. The processor had 64KB L1 cache (32KB for instructions and 32KB for data), L2 cache integrated in the mainboard, which can be from 512KB to 2MB and which works at the system bus frequency. K6-2 was launched as 266MHz version, and now it can boast 475MHz and in the near future we expect a new 500MHz version to be launched, too. There were two models of K6-2 processor: the first one worked at 266 (66x4), 300 (100x3), 333 (95x3.5), 350 (100x3.5) and 366 (66x5.5) MHz. And the second model supported 380, 400, 450 and 475MHz. It was built on the same new core as in K6-III. This new core (CXT) mainly differed from the old one by the modified cache operations. Sharptooth (K6-III). This is the first AMD processor with L2 cache integrated into the processor core. This processor closes the series of the Socket 7 devices. In fact, it is simply a K6-2 with 256KB L2 on-chip cache running at the processor frequency. Besides, there is also 64KB L1 cache (32KB for instructions and 32KB for data), and L3 cache running at the system bus frequency is located on the mainboard and can be of any size within 512KB-2MB. The processor appeared in February 1999 and was available as 400 and 450MHz versions. K6-2+. It is one of the last Socket 7 AMD processors and at the same time the first Socket 7 CPU made with 0.18 micron technology. It is supposed to have 128KB L2 cache running at the processor frequency. The core clock is expected to start from 533MHz. Of course, this CPU will boast 3DNow! support. Only mobile version is planned for launching in spring of the year 2000. Desktop version is cancelled. K6-III+. It looks as if a bit later after K6-2+ AMD were going to launch a K6-III version manufactured with 0.18 micron technology and equipped with 256KB L2 on-chip cache. Argon. This is the codename for the K7 core. K7 (Athlon). It is AMD's first project, where it had to refrain from direct copying Intel's architectures and to offer the market its own PC platform. For the today's x86 processors this CPU has a peerless L1 cache size - 128KB (64KB for instructions and 64KB for data). L2 cache takes 512KB running at half and 2/5 the processor frequency. The system bus - EV-6 - is the same as in Alpha processors, which theoretically allows making mainboards, which will support both processors. The system bus frequency is 200MHz, but its potential is almost 400MHz and up. The MMX instructions set supported by the processor is enlarged compared to K6-III 3DNow!. The device is made in Slot A form-factor. It is the first processor from AMD, which came out with a proper name - Athlon. For now you can choose from the following range: 500-850MHz. Thunderbird. Thunderbird is a socketed Athlon. Its first working sample was shown at ISSCC'2000. It supported 1.1GHz and had 512KB L2 on-chip cache running at full CPU frequency. Although Socket A remains the main form factor, at first we will still see a Slot A version. The launch is awaited in Q2 2000. Spitfire. The level of the today's technology allowed the CPU manufacturers to equip their offsprings with L2 on-chip cache of quite an acceptable size. Spitfire is none other than a low-cost consumer Socket A (Socket-462) Athlon version. Following Intel's example, they also significantly cut down the size of L2 cache. However, it is very unlikely to influence the CPU performance since it runs at the processor frequency. This device is expected to come out in Q2 2000. Mustang. This is a server version of the notorious Athlon CPU. 1-2MB L2 integrated on-chip cache. This processor is intended for 266MHz system bus and DDR SDRAM memory. The launching is planned for Q3 2000. Like Thunderbird, Mustang will be available in Slot A as well as in Socket A versions. SledgeHammer. This is the first 64bit CPU from AMD. Or at least partially 64bit. Unlike Itanium, this processor will be aimed at 32bit instructions, and not vice versa. Almost at the same time, we can expect a new bus - Lighting Data Transport (LDT) used to connect the processor with input/output devices. LDT is considered to be just an addition to EV6 or EV7 buses, and not an independent item to replace them totally. The clock speed is believed to be around 1.5GHz and up. It will come into the world in 2001. Cyrix6x86. Or M1. They used PR-rating to estimate the performance, which means that the processor performance is compared to the speed of Intel Pentium at which it has to work in order to perform on the same level as our CPU. PR-rating for 6x86 made from 120 to 200MHz. Most people were quite sure that the first processor versions were pretty famous for the errors, which often led to system crashing, and forced software developers to release patches especially for this processor. In fact, all the problems were connected with the software. Here the most "famous" ones were those written in Clipper. The rumors about some problems in Windows NT found no proof. The device has a unified 16KB L1 cache. Its system bus works at 50-75MHz. It was initially designed for Socket 5 and then appeared Socket 7 version with double voltage. MediaGX. Well, this is a certain branch of the Cyrix processor family: the first processor made with regard to PC-on-a-chip ideas. They added PCI and memory controllers to 5x86 core, integrated a graphics accelerator into the chip with the frame buffer in the PC system memory. 6x86 core is used only in the latest models. The companion chip has a PCI-ISA bridge and integrated sound. PR-rating appears 180-233MHz. The processor has a unified 16KB L1 cache. The device was manufactured with 0.5 micron technology. And today National offers two products based on this processor - Geode GXLV (0.35 micron, 166-266MHz) and Geode GX1400 (with hardware support for MPEG-2, Dolby AC3, etc.). 6x86MX. (Later it was renamed into M-II) This is a somewhat redesigned 6x86 in order to provide higher performance. L1 cache increased by four times - up to 64KB (unified), the overall performance of the processor rose as well. It acquired MMX block and started supporting separate voltage. The system bus frequency was 60-75MHz, and the PR-rating - from 166 to 266MHz. IBM also manufactured 6x86MX processors. Their 6x86MX were rated from 166 to 333 and were intended for 66, 75 or 83MHz FSB. A bit later Cyrix renamed them into M-II for marketing purposes, while IBM kept selling them as 6x86MX till their partnership was over. MII. It was the last Cyrix's processor, which manufacturing started in March 1998. It can boast a unified 64KB L1 cache, as for L2 cache, it is placed on the mainboard, like in all Socket 7 systems. It varies from 512KB to 2MB and works at system bus frequency. It supports MMX instructions. Uses PR-rating. However, the real performance in MHz is as a rule considerably lower: Cyrix MII PR366 in fact works at 250MHz. The processors are manufactured with 0.25 micron technology. Today you can get the models with PR-rating equal to 300-433MHz. Cayenne. This is a codename for the core used in Gobi and MediaPC. Gobi (MII+). This processor has two codenames simultaneously, which is pretty strange. At first, it was called Jedi, but then the codename copyright owner, Lucas Film, insisted on renaming it to Gobi. Well, Gobi is one of Cyrix's first processors intended for Socket 370 platform. Supports MMX and 3DNow! instructions. The floating point unit was significantly enhanced. The processor has a unified 64KB L1 cache and 256KB L2 on-chip cache working at the processor frequency. It was first supplied on 22 February by VIA and is known as Joshua. MediaPC. This device continues the glorious business of MediaGX. It is a Socket 7 processor working at 233-300MHz. The core is the same as that of Gobi with the added graphics accelerator and peripheral controllers. However, no one knows what's going on with this processor now. Mxi. It's a Socket/PC-on-a-chip processor based on Cayenne core, which should perform faster than MediaPC: 333-400MHz. Nobody is aware of the situation with it. Jalapeno. This is the codename for the core used in Mojave. Mojave (M3). The processor has 32KB (16KB for instructions and 16KB for data) L1 cache and 256KB L2 on-chip cache. The device is made with 0.18 micron technology and has a significantly better architecture compared to its predecessors. Supports MMX and 3DNow! instructions. It came out supporting 600-800MHz core (not PR-rating) and 100-133MHz system bus frequency. The chip will be also equipped with an integrated memory controller and 3D graphics accelerator. At present the future of this processor is rather vague because VIA too quickly entered the microprocessor market and bought Cyrix and Centaur. RisemP6. This is the first Rise processor, which is intended mostly for notebooks using Socket 7 processors. As a result, it emits very little heat. The processor has 16KB L1 cache (8KB for instructions and 8KB for data), and L2 cache placed on the mainboard, which can be from 512KB to 2MB and works at system bus frequency. It supports the additional MMX instructions. To estimate the performance of its processors Rise, like Cyrix, resorts to PR-rating. This one is rated from 166 to 366MHz. mP6 II. This processor differs from mP6 the same way K6-III differs from K6-2. The same core with 256KB L2 on-chip cache. They have also promised SSE support and performance starting from PR-200 and higher. However, in August 1999 they announced that all the plans concerning the processor launching were cancelled because of the significant costs increase after they had added L2 on-chip cache. Tiger. This is a mP6 II for Socket 370 platform. It is provided with 16KB L1 cache, 256KB L2 cache working at the processor clock frequency. The samples will be supplied starting from the end of 1999. CentaurWinchip C6. This processor was initially designed for low-cost PCs, and hence its performance was lower than that of its main competitors. It supports 60, 66, 75MHz system bus, and is designed for Socket 5 platform. The device was made with 0.35 micron technology. It supports MMX instructions. The processor was launched in October 1997 and worked at 180-240MHz. Winchip-2. This processor was manufactured with 0.25 micron technology. It is equipped with 64KB L1 cache (32KB for instructions and 32KB for data), and with L2 cache placed on the mainboard and can have the size from 512KB to 2MB. The processor supports MMX and 3DNow! instructions and is developed for Socket 7 platform. It works at 200-300MHz. The main difference between Winchip and this CPU is that the latter performs floating point operations considerably faster. Besides, they also introduced 100MHz FSB support. The processor appeared in November 1998. Winchip-2A. It's a Winchip-2 with the eliminated error in 3DNow! realization. Winchip-3. The processor has 64KB L1 cache (32KB for instructions and 32KB for data), 128KB L2 on-chip cache working at the processor frequency and L3 cache placed on the mainboard, which size can be from 512KB to 2MB. This processor was planned for the first half of 1999 with the working speed starting from 300MHz and higher. However, the launching of this processor seems to be cancelled because VIA too quickly entered the microprocessor market and bought Cyrix and Centaur. Winchip-4. This device was planned for launching in the end of 1999 with the working frequencies of about 400-500MHz, and then as soon as they change to 0.18 micron manufacturing technology - with the frequencies equal to 500-700MHz. We also expected the form-factor to be changed. VIAJoshua. The first VIA processor planned for launching turned out Cyrix's Gobi design acquired together with the company. Go to Cyrix section for more details. The launch is scheduled for 22 February. Samuel. Winchip-4 core, which VIA inherited from Centaur, the chip working at 500-700MHz. This piece is very likely to be manufactured with 0.18 micron technology. It is supposed to become Timna's direct competitor, because they also expect to integrate a graphics core and North bridge. This CPU will make use of SIMD 3DNow! instructions set. The probable form factor is Socket370. The processor is scheduled for Q2 2000. Cyrix III. This brand will be used for Joshua processor, when it becomes available for purchase. TransmetaCrusoe. On 19 January Transmeta finally summed up its five-year business and announced Crusoe processor. The company decided not to compete with Intel and AMD in the spheres where they are really strong, and positioned their CPU as the best mobile solution, HPC, etc. At first, the processor will be available only in two versions: 333-400MHz TM3120 and 500-700MHz. The first one has 96KB L1 cache and the second one - 125KB L1 + 256KB L2 cache. The power consumption varies from 10-20mW to 1-3W depending on the task carried out at the moment. The chips are expected to start selling in the second half of the year 2000. <%BANNER[banner_468x60_f]%>
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