One Core Is Good. Two Cores Are Even Better!

The main event of the next year 2005 in the processor market will be the announcement of the CPUs based on new dual-core architectures. Our new article will introduce to you the new characteristics and peculiarities of the upcoming dual-core CPUs in great detail.

by Ilya Gavrichenkov
12/24/2004 | 12:26 PM

One of the major events of the upcoming year 2005 in the CPU market should inevitably be the release of the dual-core processor architecture. To cut the long story short, the idea behind dual-core CPUs is very simple. One processor physically based around a single semiconductor die will feature two equally functional processor cores.

 

In other words, it will be a dual-processor system packed into a single processor casing. Right now the processor developers consider this way of increasing the processors performance and functionality to be very promising. As a result, not only the two leading CPU developers, such as AMD and Intel, but also the VIA Company are planning to start introducing single-silicon dual-core CPUs in the upcoming year 2005.

In fact, the idea to put two processor cores onto a single physical die is not that new in this industry. In the end of last century the high-end multi-processor server developers, such as HP or IBM already pointed out the potentially prospective possibility of designing a CPU including two computational dies. As a result of significant progress made in this field there appeared dual-core HP PA8800 and IBM Power4 processors, which have been successfully used in different server solutions like IBM eServer pSeries 690 or HP 9000 until nowadays.

However, we wouldn’t call these products mass products. Since they are pretty expensive, they have never got that widely spread. Why? Well, take for instance the die size of the dual-core IBM Power4 processor with 128MB L3 cache memory, which is equal to 115x115mm. So, I would not call processors such as IBM Power4 and HP PA8800 “real” predecessors of the upcoming dual-core processor solutions from Intel and AMD.

Nevertheless, the mere idea of splitting the computational process into several parallel threads within a single CPU is not that new even for the desktop solutions. Intel undertook the first steps in this direction in the year 2002, when they first launched their Xeon and Pentium 4 processors supporting Hyper-Threading technology. The idea of Hyper-Threading technology implies that the processor based around one physical computational die emulates two independent CPUs working in SMP mode (symmetric multiprocessing).

In fact, the CPU supporting Hyper-Threading technology has a very small number of duplicated functional units: registers (including general purpose and managing registers), Advanced Programmable Interrupt Controller (APIC) and some service registers such as Next Instruction Pointer, for instance. All other resources, including caches, execution units, branch prediction logic, bus controller, etc. are shared between the two logical CPUs. This trick allows single processor silicon to process two threads of calculations simultaneously, because the second virtual core uses processor resources undemanded by the first virtual processor. Contemporary CPUs equipped with a few parallel execution units turn out more efficient fur to Hyper-Threading technology, because it allows loading the execution units more evenly.

Today, when most operating systems have already become multi-taking, the use of second processor helps increase the system performance quite noticeably. Besides, the support of Hyper-Threading technology in Intel processors stimulated the arrival of new quality software taking advantage of the progressive features like two simultaneously working parallel computational threads. This way we can state that the market has already prepared pretty well for the next significant step towards multi-core processor architectures.

However, before we begin our story of the dual-core processors that are to come out next year, I would like to say a few words about the actual benefits of the dual-core solutions for the processor developers and for the entire market.

First of all, the introduction of dual-core technology is another efficient way to increase the processor performance. Since the actual CPU performance is the processor working frequency multiplied by the number of instructions the given CPU can process per clock cycle, the introduction of dual-core architecture should double this parameter, because adding another core will automatically double the number of execution units in the CPU. I have to specifically stress here that if you want to achieve maximum performance you should make sure that all these execution units available in two processor cores are used to the full extent. However, this is the primary concern for the software developers, and not for the CPU designers. Therefore, it is evident that the dual-core processor architectures will ensure actual performance increase only if they receive proper support on the software side. Besides, the traditional way of increasing the CPU performance by raising its working clock frequency has now stumbled upon pretty serious obstacles, caused by technological problems in the first place.

Secondly, the use of dual-core architecture should also increase the overall processor functionality, which is also a very important factor, especially for the company marketing strategy. The thing is that the introduction of dual-processor architectures and launching of the next generation Microsoft Longhorn operating system should stimulate the development of new virtualization technologies. Both AMD and Intel believe that they are going to become a major distinguishing feature of the next generation computer systems, and thus are very important. According to independent analysts, these technologies will be actively used in the upcoming PCs in 2006-2007 and will bring their features to a completely new level.

Different virtualization technologies, which are currently known under various codenames, such as Intel Vanderpool, Intel Silvervale and AMD Pacifica, but are based around the same principles, are being developed in order to allow emulating several virtual systems within a single physical computer. In other words, these technologies should allow the users to use more than one operating system on their PC, so that each OS could be busy solving its specific matters. The difficult part about the implementation of this idea is the fact that all operating systems work within a “zero circle”, i.e. they interact directly with the system hardware. However, the new virtualization technologies that I am talking about right now should make it possible for several operating systems to share the hardware resources of the single physical machine without any performance limitations.


Vanderpool technology

As you remember, at the IDF last year Intel already demonstrated a PC with Vanderpool technology in action. There were two virtual systems running on that PC, each with its own operating system. They were changing the OS settings and installing the drivers on one virtual computer, while another virtual computer worked as an entertainment center playing back an animated movie. And during the movie playback they rebooted the first virtual system without affecting the movie playback on the second virtual system at all. So, both these tasks were performed simultaneously and didn’t interfere with one another. This way, Vanderpool should support the so-called “division of labor” on the upcoming computer systems designed according to Intel’s digital home concept.

Dual-Core Architecture from AMD

The today’s leader in the dual-core architecture development, just like in many other innovative initiatives, is AMD Company. The processor developer and manufacturer was the first this year to reveal very clear plans concerning dual-core processor architectures and to demonstrate a working prototype system based on a solution like that. Moreover, we have every reason to believe that the first processor with dual-core architecture, which will go into mass production, will be none other but AMD Opteron.

AMD’s dual-core development program was established long time ago and has been persistently put into life since the very first day. AMD started talking about the upcoming integration of two cores with AMD64 architecture onto a single silicon die back in 1999, when they worked on this particular architecture. This way, we assume that AMD had already kept in mind the peculiarities of the dual-processor architecture when they just started working on their Athlon 64 and Opteron CPUs. That is why they should have no serious problems with setting up the production of dual-core processors.

It is also quite evident that they could have possibly built a dual-core CPU around the Hammer die, since this die already has a fast Hyper-Transport bus, which could serve to connect two processor cores within a single physical package. However, AMD didn’t go that way. They are going to use more efficient design, which will allow sharing the resources between the two cores in a more efficient way and will ensure their more productive interaction.

Both cores of AMD’s dual-core CPUs will feature completely independent execution units and cache memory. In other words, each of the two cores within a single processor from AMD will have its own L2 cache, so the company engineers will have to pay special attention to their coherency. However, I don’t think this is going to become a really serious problem for AMD: MOESI protocol (Modified, Owned, Exclusive, Shared, Invalid) developed in the times of AMD Athlon MP processors can pretty much guarantee proper cache memory coherency not only for different CPUs of an SMP system, but also for different processor cores.

As for shared resources, they include all other units, which are actually performing the North Bridge functions. Among them are dual-port System Request Interface, which actually connects the processor dies within a single silicon, Crossbar Switch, which connects both processor cores with the shared resources, and the resources to be shared between the cores (up to three HyperTransport buses and the memory controller). In other words the dual-core AMD processor will feature individual cache memory for each of the cores, but at the same time will be equipped with only one memory controller, which will be working with both cores simultaneously.

The first dual-core AMD processors will be manufactured with second generation 90nm production technology, i.e. with SOI and Dual Stress Liner technologies involved. Note that at this stage the cores will not actually undergo any dramatic architectural changes compared with what we have now. It means that most of the features of the first dual-core AMD processors will be identical to those of the currently available CPUs with AMD64 architecture. In particular, these dual-core processors will use 1GHz HyperTransport bus to connect to the chipset and will feature two memory channels to work with DDR SDRAM. However, only due to the absence of radical innovations on the interface level, the upcoming dual-core processors from AMD will be compatible with the regular platforms supporting current single-core Athlon 64 and Opteron solutions.

In fact the only thing that the old platform may require in order to fully support new dual-core processors, is the BIOS update. Since all the logic ensuring successful interaction of the processor cores is inside the CPU, these dual-core solutions can actually work with any chipset.

However, the upcoming dual-core solutions from AMD will still boast a few interesting innovations. First of all, these processors will support 10 new SSE3 instructions, which have been supported by Intel Pentium 4 since the launch of Prescott processor core. Here I would like to stress that this list of SSE3 instructions will not include MONITOR and MWAIT commands supported by the Pentium 4 Prescott, because they serve to manage Hyper-Threading technology, as well as LDDQU command, which was introduced in AMD’s 3DNow! Instructions set long time ago. Secondly, the first dual-core AMD processors will have 4 write combining buffers instead of 2. And thirdly, AMD is going to introduce additional power saving technologies for dual-core processors.

AMD is going to announce its first dual-core processors in mid 2005. They will be launched within the Opteron processor family. In other words, AMD’s strategy implies that they will first introduce dual-core solutions in the server and workstation markets. These are exactly the fields where dual-core processor architecture should be most welcome in the nearest future, according to AMD. First dual-core Opteron CPUs will be compatible with Socket 940 systems, and the total amount of their L2 cache memory will reach 2MB (1MB for each core).

Manufactured with 90nm technology, these CPUs will consist of about 205 million transistors, however, the die size of the semiconductor silicon with two cores will not get any bigger compared to the 130nm SledgeHammer core currently used in AMD Opteron processors. Note that the today’s Opteron CPUs include 105.9 million transistors. Which means that despite the shared resources, the new dual-core architecture will turn out 93-94% more complex compared with a single-core one.

There is another piece of evidence that AMD sticks to the initial plan in terms of dual-core architecture development. The first dual-core Opteron CPUs have already been showcased to the general public. In the end of August AMD showed a four-socket HP ProLiant DL585 server with four dual-core Opteron CPUs manufactured with 90nm technological process. After the corresponding BIOS update this system designed for four Socket 940 processors managed not only to recognize the new processors, but worked with them as a fully-fledged 8-way system.

As for the working frequencies of the dual-core solutions, it is evident that the die gets more complex when we add the second process core, thus the actual working frequency should get somewhat lower compared to the frequencies contemporary single-core Athlon 64 and Opteron processors can work at today. Right now there are no data about the working frequencies of the first dual-core AMD CPUs, but the dual-core Opteron solutions we have just told you about worked at 1.6GHz. I believe that the final working frequencies of the first officially announced dual-core CPUs will hardly be much higher than that. The thing is that AMD has set pretty strict requirements to the maximum heat dissipation of the new dual-core processors. The upcoming dual-core CPUs are claimed to fit into the same thermal interval as the today’s Athlon 64 and Opteron CPUs do. It means that the maximum thermal design power of the new promising products from AMD will be below 95W.

Of course, lower clock frequency will result into noticeable performance drop in those applications, which make no use of multi-threading algorithms. AMD is perfectly aware of this fact that is why they do not push their dual-core solutions into the desktop market that hard. Server and workstation software, however, has been optimized for multi-processor configurations for a long time now. That is why AMD is going to start promoting dual-core architecture for the Opteron family in the first place. And this is going to be a pretty successful move. According to the first benchmark results, even despite the 600MHz-1000MHz lower working frequency of the dual-core CPUs compared with the working frequency of the single-core ones, their performance in applications supporting multi-threading will not suffer.

In SPECint2000 benchmark the system based on two dual-core processors proves about 45% faster than a similar system based on two single-core processors working at 1GHz higher actual clock frequency. If the frequencies difference drops down to 600MHz, the performance gap between the dual-core and the single-core system rises to 55-60%. We observed similar results in SPECfp2000 benchmark. Here the dual-socket system with two dual-core CPUs defeated a similar system with two single-core CPUs by 25-30%, while the working frequencies of the processors differed by 1GHz. When the working frequencies differed by only 600MHz, the performance of the dual-core system turned out 35-40% higher than that of the single-core system. Purely server benchmarks also indicate that high working frequencies are not a determinative for the systems based on dual-core processors. For example, in JBB2000 benchmark a system with dual-core processors outperforms a system with single-core processors by 30%, while the working frequencies of the CPUs in these systems were 1GHz different; and by 45% when the single-core CPUs worked at 600MHz higher clock rate than the dual-core ones. Another benchmark called WEB99_SSL demonstrated almost the same results. So, high clock frequencies are not a must for dual-core Opteron processor family.

According to AMD’s current roadmap, they are going to introduce dual-core Opteron processors in the second half of next year. Note that these CPUs are most likely to be announced not only for two-way systems, but also for single-processor, four-way and even bigger systems. Opteron 1XX series will be continued by dual-core CPUs aka Denmark, Opteron 2XX series will acquire dual-core CPU known under Italy codename, Opteron 8XX product line will have a new dual-core solution called Egypt. However, AMD is not planning to stop at the Opteron family. Closer to the end of the year 2005 they are going to introduce the first dual-core desktop processor. This CPU is most likely to appear first in the Athlon 64 FX family targeted for the pretty narrow enthusiast market segment, and in the meanwhile it is known under Toledo codename.

Later on AMD is going to increase the share of dual-core solutions among its CPUs. So, AMD’s dual-core processors should not be regarded as a purely niche product: these solutions will be invading all market segments with the time. Therefore, AMD has already figured out the strategy in this direction for more than one-year period of time. Of course, they will be shifting to finer production technology of 65nm in the future, which will allow designing a CPU with more than one core per single physical silicon. Moreover, AMD is going to enhance the processor memory controller by providing it with DDR2, DDR3 and FB-DIMM support. They will also start using faster HyperTransport 2.0 bus and implement efficient technologies reducing heat dissipation and power consumption of the new processors by disabling the unused processor cores, which will certainly allow using AMD multi-core solutions in the mobile systems as well.

Dual-Core Architectures from Intel

Intel’s plans this year have changed pretty dramatically. If the company used to stake the growing clock frequencies of their solutions in the first place, then today it turned out that they can no longer rely on this measure. The processor core architectures developed by Intel engineers and used in Pentium 4 and Xeon processor families were initially supposed to be able to work fine at higher clock frequencies, that is why they were provided with a long execution pipeline. However, further core clock frequency increase stumbled upon some fundamental problems on it way. These problems revealed themselves after Intel moved to 90nm production technology: namely, the new Prescott based CPUs didn’t work that well at higher clock rates even though their execution pipeline grew significantly longer. The processor overclocking couldn’t pass by the heat dissipation and power consumption limitations, leakage current growth and tangible slowing down of the performance gains as the core clock frequency increased. All this pushed Intel to revise their plans significantly.

So, in the coming year Intel is going to focus first of all on increasing the functionality of its solutions rather than speeding up their performance. This new concept suits perfectly well for the dual-core processors, which should become a basis for the new generation of computers supporting virtualization technologies. Moreover, in some cases dual-core architectures can also ensure the performance growth of the systems based around them. That is why Intel got so much carried away by the dual-core processor concept, when they realized that further clock frequency increase with the current architecture is no longer possible. Moreover, since dual-core architectures are being introduced so rapidly, Intel has even given up the continuation of the Tejas product family development. According to Intel’s engineers, the dual-core concept can appear much more fruitful than any further investment into the regular NetBurst CPUs.

Intel has truly Napoleon’s plans concerning the introduction of the dual-core processor architectures in different market segments. While in 2004 only 65% of the desktop systems support virtual dual-core architecture provided by Intel’s Hyper-Threading technology, and in the mobile market there were simply no solutions of the kind at all, Intel hopes that in the future the situation will change nicely. By 2006 they expect over 70% of the desktop processors and over 70% of the mobile CPUs to be based on dual-core architecture. As for the server CPUs, by the year 2006 over 85% of these solutions will be based on dual- or even multi-core architecture.

Unlike AMD’s plans, Intel has a different strategy how to bring these processors into the market. The Micro-processor giant is not going to start with the workstation and server markets, but with the desktop solutions. In fact, this is a pretty evident and logical plan. It is exactly in the desktop segment that Intel is falling most behind its major competitor – AMD. While AMD has successfully managed to significantly speed up its desktop solutions this year, Intel’s processors got just a little bit faster in terms of clock frequency growth because of multiple technological troubles. That is why Intel is hurrying so much with the development of dual-core desktop solutions: the first CPUs based around new architecture should appear in the market in Q3 2005 already. Today these CPUs are known under Smithfield codename, and they will be targeted as competitors to top desktop AMD CPUs, which performance ratings should reach 4200+ by mid next year.

The transition to dual-core architecture in desktop Intel processors is expected to allow this company to significantly increase the performance of its solutions. Moreover, the effect from this performance upsurge will remain there for the next few years, until four- and more-core architectures arrive into the marketplace.

Since Intel simply has no time (or maybe no desire) to develop the new architecture, which would be better fit for the dual-core processors, Smithfield solution will be based on two Prescott cores manufactured with 90nm production technology. Smithfield will actually consist of two independent Prescott cores combined on a single silicon die. In fact it means that each of the two Smithfield cores will use its own execution devices as well as its own independent 1MB L2 cache. The CPU will also feature its own arbiter, implementing the dual-core processor interface with the only 800MHz Quad Pumped Bus. Since almost all the Prescott processor functional blocks will be duplicated in the upcoming Smithfield solution, and there will be one more extra arbiter added to them, the Smithfield die size will be not 2 but 2.1 times bigger than that of the Prescott.

This tremendous die size increase will automatically result into the increase in the heat dissipation of this CPU. However, the heat limitations imposed by the Intel’s LGA775 systems imply that the maximum thermal design power of Smithfield CPUs cannot go beyond 130W. This way, just like the dual-core AMD processors, the new dual-core solutions from Intel will work at lower clock frequency than the similar single-core ones. As far as we know today, the maximum working frequency of the Smithfield processors will make 3.2GHz, which is 16% lower than the maximum frequency a Prescott based CPU can actually work at.

However, it is pretty hard to claim that the performance of Smithfield based processors will exceed that of the single-core ones. AMD, for instance, has every right to claim a notable performance increase as a result of the transfer to dual-core processor architecture on single physical silicon, because they are planning to begin from the server and workstation market. The applications for this type of computer systems are initially developed for SMP-systems, which support multi-threading. As for the dual-core Smithfield processor, it is going to turn up in a totally different type of systems: regular desktops. And even though major operating systems for the desktop PCs have been supporting multi-threading for a long time now, far not all the applications really make use of it. The worst situation appears to be with games. There are few games out there that take real advantage of multi-threading, which can lead to the fact that Smithfield based CPUs will turn out slower than their single-core Prescott based predecessors in a number of desktop applications. In order to diminish the negative influence of this incident, Intel has even given up the launch of the 4.0GHz Prescott based Pentium 4 processor. However, as we assume this sacrifice is still unable to solve the problem.

In order to make Smithfield more attractive for the users, Intel will introduce a few other new technologies besides the dual-core architecture. It is absolutely clear that Smithfield processors will support EM64T technology (Intel Extended Memory 64 Technology), 64-bit extensions for the x86 architecture being a functional analogue to AMD64. It is also evident that Smithfield processors will support Intel SpeedStep Technology (aimed at reducing the heat dissipation by lowering the CPU working frequency when the workload is not that high) and Execute Disable Bit (allows creating better shield protecting the operating system against harmful software). In fact, you will also be able to see these technologies supported in the single-core Pentium 4 processors, which are scheduled to come out next year. As for the unique peculiarities of the Smithfield CPUs, I could list among them the support of Vanderpool virtualization technology and LaGrande security technology in the first place. However, we are very unlikely to be able to take advantage of these technologies until Microsoft Longhorn OS comes out, that is until 2006. therefore, Vanderpool and LaGrande should officially be announced only when the production of Smithfield CPUs moves to 65nm process.

Speaking about different technologies implemented in dual-core Smithfield processors, we cannot disregard the fact that the “virtual dual-core” Hyper-Threading technology will be disabled in this solution. The reasons for that are pretty evident: it is not an easy task to arrange correct distribution of data streams between the physical and virtual cores, which will definitely require additional execution units to be introduced in the CPU. Of course, if the application creates two computational threads, it is clear that each should be allocated to an individual physical core. But what should be done if there are three threads, for example? In order to prevent the already complex design of the dual-core Smithfield from becoming even more complex, and to avoid the launch delays caused by the necessity to complete additional engineering research and development, Intel simply decided to give up Hyper-Threading in their upcoming Smithfield. So, since each of the two Prescott cores used in Smithfield CPU does potentially support Hyper-Threading, it will be disabled in the dual-core Smithfield processor.

Just like the dual-core AMD solutions, the upcoming Smithfield CPUs will be compatible with the currently existing infrastructure. Due to the built-in arbiter responsible for the communication between the two internal cores, the new dual-core processors will be able to work in the same mainboards, as we are bow using for single-core top Pentium 4 processors on Prescott core. Therefore, Smithfield will support 800MHz Quad Pumped Bus and will be designed for LGA775 form-factor. However, even though Smithfield is compatible with the i925/i915 based mainboards, Intel still recommends using it in the platforms based around the new upcoming sets of core logic called Glenwood and Lakeport. The reason for that is first of all the ability of these new chipsets to support large amount of system memory (up to 8GB), which may be essential for dual-core processors supporting EM64T technology.

As for the actual specifications of Smithfield based CPUs, which will arrive into the market next year, they have all been known for a long time now. In Q3 2005 Intel will launch three processors from this new family, which will supposedly be marked with the following indexes: x20, x30 and x40. It looks like the only significant difference between these three dual-core CPUs is going to be their working frequency. The top x40 model will work at 3.2GHz, the x30 model – at 3.0GHz and the x20 model - at 2.8GHz. Moreover, the x20 processor positioned as a Low-End dual-core solution compatible with a lot of mainboards available in the market, will not support Intel Enhanced SpeedStep technology.

This processor family including three models is going to last for quite a while. Intel is very unlikely to release any faster CPUs within this family, because of the thermal limitations. Therefore, we can expect new dual-core solutions from Intel to arrive only when they master the 65nm production technology, i.e. not earlier than in H2 2006.

For this period of time Intel plans to announce the next generation of dual-core processors for desktop PCs aka Presler. Due to the use of  65nm production process the die size of these CPUs will be below the 140sq.mm, while the die size of Smithfield core is around 240sq.mm.

While Intel is focusing on the desktop dual-core processor solutions, as their utmost plan for the year 2006, they seem to have completely forgotten about the server and workstation markets. Even though their major competitor, AMD Company is going to introduce their dual-core Opteron processors in the middle of the next year, we will not see any dual-core Xeon CPUs from Intel next year. Even despite the fact that these CPUs have been using slightly modified desktop processor cores for years. The major reasons for that are definitely the necessity to invest more time and effort into the more thorough Smithfield development and certainly the absence of the appropriate chipsets for the server and workstation platforms.

The first dual-core Xeon processors are scheduled to come out in early 2006 and are known under the codenames of Dempsey and Paxville. Dempsey will be targeted for dual-socket configurations while Paxville – for multi-socket ones. Despite the relatively similar architecture, the major difference between these two processors and the dual-core Smithfield will be the support of Hyper-Threading technology, which will allow these processors to process up to 4 data streams simultaneously. To support Dempsey and Paxville, Intel plans to release two new chipsets in the beginning of 2006: Blackford and Greencreek. They differ from the predecessors by the ability to work with large amounts of system memory due to the fact that they support Fully Buffered DIMM (FB-DIMM) and new Dual Independent Bus, which allows building the point-to-point topology connection between the chipset North Bridge and each of the physical processors. This innovation can increase the performance of Intel multi-processor systems quite tangibly, since the previous generation multi-processor systems from Intel used to share the same bus between all the CPUs of the system.

However, Intel will still pay some attention to the server market in 2005. Although, the dual-core solutions from Intel launched in 2005 will be based on IA-64 and not on x86 processor architecture. In other words, next year we will see not only the new dual-core Smithfield but also the new Montecito CPU from Intel Itanium family.

The major principles used for the design of Montecito processor, are actually very similar to those used for any other dual-core design. Therefore, if I decided to describe Montecito briefly, that will be a chip with two Itanium 2 cores on a single physical die, which are managed by the internal arbiter and boast a larger L3 cache. Just like in Smithfield processors, the cache memory in Montecito is split between the two cores. And it is true not only for the L2 cache, but also for the L3 cache memory. As a result, Montecito processors will have 24MB L3 cache (12Mb for each core) and two pairs of L2 cache memory: 1MB for instructions and 256KB for data for each. So, the total cache memory of a dual-core Itanium 2 successor will be 26.5MB, while the die will consist of 1.72 billion transistors. Montecito processors will be the first CPUs in the Itanium family manufactured with 90nm production process. The gigantic die of these processors will be 580sq.mm big. Montecito CPUs are expected to launch at 1.7GHz core clock frequency, while their heat dissipation should stay within 100W range, which will make them look much better than any other dual-core IA-64 Intel processors.

Due to Montecito’s ability to split the calculations between the two parallel cores, it will also support something similar to Hyper-Threading, which will increase its performance by 1.5-2 times compared with that of the Itanium 2 9M. Moreover, this processor will also support such new technologies as Pellston (to ensure the reliable functioning of the cache memory, the processor will be capable of disabling the failing cache lines) and Foxton (will allow speeding up the CPU in case it is running in good thermal conditions, and slowing it down once its gets too hot).

In 2006 the dual-core Montecito family will get further continuation. Intel will launch better value Itanium processors for dual-socket systems known as Millington alongside with their lower-voltage modification. Then Montecito and Millington will be transferred to 65nm production technology and will change their codename to Montvale. By the way, Intel is going to take more advantages of the dual-core technology in the future when they will work harder on new IA-64 solutions. In the year 2007 already, the company engineers promise that Itanium processors will contain twice as many cores as the Xeon processor family. It looks like Intel is trying to get on the way towards four-core processor architecture for its Itanium 2 successors.

I would like to stress that Montecito is closer to release than any of the other dual-core processors from Intel. There already exist working samples of this CPU based on A0 silicon stepping. Therefore, Intel even managed to showcase a four-way server based on these processors capable of processing up to 16 simultaneous streams of data.

If Intel is planning to start producing desktop and server dual-core processors with the 90nm technological process, then in the mobile segment they are first going to mast the finer 65mn production technology. In fact, this is not at all surprising, Intel doesn’t have to rush anywhere in the mobile market. The current Pentium M architecture makes all Intel’s customers pretty happy, as it demonstrates high performance and low heat dissipation. Nevertheless, next mobile platform from Intel aka Napa will be based on a dual-core CPU with Pentium M architecture.

In fact, Intel is going to push dual-core processors into the mobile market for completely different reasons than those that inspired them to go into the desktop and server segments with their dual-core architecture. This is another reason why there is no rush with the development of the dual-core mobile solutions. The major goals set for the dual-core mobile solution developers are lower heat dissipation and higher functionality of these processors.

The first dual-core notebook CPUs known as Yonah will be released in the end of 2005-beginning of 2006. They will be based on Pentium M cores, although they will be not just a simple concatenation of the Dothan cores modified taking into account the potential of the new production technology. Unlike all other dual-core processors, Yonah will have shared 2MB L2 cache memory for both. This way, Yonah developers do not face any cache coherency problems.

In order to reduce power consumption and heat dissipation, the new Yonah processor will support special technology, which will allow disabling one of the cores in case the processor load is low. This feature will make Yonah a very economical CPU, even more economical than the today’s Pentium M on Dothan core. In fact, the second Yonah core will join the first working core only when the CPU workload reaches its peak, which is not going to happen that often. Of course, this technology will not eliminate the support of Intel Enhanced SpeedStep: Yonah will also support it. The heat dissipation of these processors should stay below 40W, while the core frequency will exceed 2.0GHz. Moreover, Intel promises that Yonah will boast LaGrande and Vanderpool technologies as well, which should definitely enrich its functionality.

Since Yonah processors are still quite far away, there is not that much detailed technical info about them. For instance, we do not know their working frequencies. As for the physical die size, the info is also pretty vague still. The die size of the Yonah processors is expected to be about the same as that of the Dothan core, even though there will be the same amount of cache memory onboard, but the production technology used for the new solutions will be finer. The implementation of the shared cache memory and dynamic core disabling technologies is a pretty complicated task, therefore Yonah will have considerably more transistors than the today’s Dothan CPU.

The new mobile dual-core processor from Intel aka Yonah will arrive together with the entire new platform, including new Calistoga chipset and new wireless Golan component. This way the mobile Napa platform including Yonah processor will acquire DDR2-667 SDRAM and 667MHz processor bus support.

Dual-Core Architecture from VIA

The hunt for dual-core architecture carried away not only the leading processor developers. VIA Company, which offers niche solutions for inexpensive and economical systems decided to follow in the footsteps of Intel and AMD and announced their plans regarding the introduction of their dual-core solution in mid 2005. Although we have to point out right away that VIA’s approach to dual-core processor architecture designs is completely different from what the industry leaders have offered.

In fact, the positioning of the upcoming dual-core solution from VIA is also different. While Intel and AMD will offer their dual-core CPUs as high-performance server, desktop and mobile solutions, VIA is going to target these processors for the low-cost small servers or even compact clusters.

The upcoming dual-core processor from VIA will not be built on a single silicon die with two processor cores. The company engineers will try to combine two semiconductor dies with processor cores within a single processor package. This way it will not be a dual-core solution in the full meaning of this word. In fact, they will simply design a dual-processor system in a single package.

Nevertheless, this can turn out a very interesting solution for its market. Especially taking into account that VIA’s dual-core processors will be based on a prospective Esther cores due to be released in May 2005. These 32bit CPU cores will be produced by IBM with 90nm technological process and will boast very low power consumption. The working frequency of the first Esther processors will be about 2GHz while the maximum heat dissipation will be only 15W. Esther CPUs will also support VIA’s brand name PadLock technology accelerating the hardware RSA encoding and NX-bit.

As for the formal features of the upcoming VIA core, we can say that Esther will have 128KB L2 cache, which will make its die only 31.7sq.mm big. The CPUs will use 800MHz Quad Pumped Bus and should theoretically be compatible with Pentium 4 infrastructure. Also VIA is planning to make their Esther support SSE2 and SSE3 SIMD instructions.

Note that the performance of VIA’s upcoming Esther processors will be quite low: this 2GHz core will be able to compete successfully only with Celeron 1.2GHz, which once again determines the specific application field for this type of solutions and dual-core CPUs based around Esther architecture.

Conclusion

It is evident that the year 2005 is going to become an important milestone for the multi-core architectures evolution. All major processor developers will have not only to present their dual-core CPUs but also to clearly describe their ongoing plans in this direction. Of course, at first dual-core processors will receive a very warm welcome in all market segments. But as the time passes and the OS and software developers adapt more to the new working conditions, the multi-core processor architectures can lead the industry to the new performance levels.

Moreover, the appearance of dual-core processors and solutions with additional new features once again indicate that the clock frequency race is no longer acute. I believe that in the near future we will not select processors according to their clock rates but will take into account the whole lot of various characteristics, including not only the working frequency, but also the number of processor cores, cache memory size, additional technologies support and maybe more.

So, it is quite possible that the entire next year will be very interesting for all of you who follow the events in the computer market regularly. The CPU market will go through a lot of dramatic technological changes, which we’d better get ready for in advance. However, it is the marketing companies who should pay due attention to this sort of preparations in the first place. Our task is to let you know about these coming changes as early as possible. Hopefully, this article fulfills this goal of ours :)