X-bit labs

Intel Developer Forum Spring 2005: Day 2 Coverage (page 9)

Category: Editorial

by Anna Filatova

[ 03/02/2005 | 11:53 PM ]

Server Product Roadmap

Dempsy

It is a dual-processing server processor. It is based on the 65nm process technology. It supports HT, so there are 4 threads in this particular processor. It also features 64-bit support and Execute Disable Bit. The CPU will be designed for the server based LGA771 socket. The bus will allow only three loads.

Paxville

For multi-processing systems Intel will have the Paxville processor. It will have is two independent cores and two independent L2 caches, but there will be one difference here: it will be designed on a single piece of silicon. So, the two cores will share one bus interface. As a result, the bur will allow only two loads.

This solution will be available the same time frame as Dempsy processor, namely in Q1 2006.

Montecito

The dual core Itanium processor will support 4 threads and will be designed with 90nm technology. It’s got two independent L2 instruction caches each 1MB big. And there will be two L3 caches. It will be designed on a single piece of silicon, but there is no single line you can draw to cut the two cores apart, like we could do on the previous generations of CPUs discussed above. It is pretty highly integrated: we have caches on the top and bottom, and the execution cores are kind of joined together. This die has 1.7 billion transistors which is a huge number. (Compare with the 29,000 transistors in the 8088 processors dating back to 1979, when IBM launched their first PC. Pretty impressive, eh? :).

It will be available in Q4 2005.