by Anna Filatova
03/02/2005 | 11:53 PM
Today we will be talking a lot about the desktop and mobile solutions from Intel. But before we start I would like to stress that the entire forum, all the sessions and classes were conducted under the sign of unleashed information on the new dual and multi core solutions from Intel. Today we are going to reveal the most interesting architectural and technical details of the new dual-core designs, which are now present within all the major initiatives that Intel introduced and talked about at the Forum.
<%BANNER[article]%>And you know what these initiatives are: Digital Home Concept and Digital Office Concept from the desktop and mobile prospective.
The first keynote today was dedicated to mobile platforms. Sean Maloney, Executive Vice President and Manager of Intel Mobility group was talking about Intel end-to-end wireless networks and wireless clients technology, which continued to fuel the market growth of mobile computing. It is true, the mobile devices market is exploding lately. Besides the notebooks, which have always been the #1 system in the mobile market segment, we also see a lot of other device types picking up. Cell phones, PDAs, handhelds. The overall industry focus is moving towards these products which are at the crossroads of PC and consumer electronics.
Mobility itself is driving the requirements for more performance and innovation. The idea is to address the mobility market in an optimal way. There are basically three major tendencies in the today’s mobile market that determine its growth and expansion:
Right now you may see that data phones are overtaking voice phones. But the major strategy is still to expand so that the products could cover all market levels. And to be successful these products should also acquire full support on the software side, which we see happening. For example, the today’s cell phones already have real time operating systems running on them.
Besides, the flash memory technology which is very important for the growing mobile market got at another evolutionary stage of its development. According to Intel, there are already 90nm flash wafers produced and they also have first 65nm flash engineering samples at their disposal.
All the above mentioned breakthroughs in the technologies that are essential for the mobile market have are leading to one result, which is actually implied by the tendency. When Intel says that phones get smarter they actually mean that there is no more evident interception between the laptop and the phone. It is very likely that at the current pace of the technological advancements you will have a phone in 2-3 years that will be able to offer you good camera quality, and will know to jump on and off high-speed networks. In this respect it is one of the primary goals to make these devices communicate with one another, namely to make the notebook and phone much more aware of each other’s presence and make them able to communicate with one another in an easy one-click way.
This is the second global tendency in the today’s mobile market. Wireless technology is picking up real quick:
Here Intel first of all mentioned the new platform that would bring ultimate wireless performance to the mobile segment.
It is the Napa platform due in 2006. It will be based o Intel’s first dual-core mobile Yonah CPU with mobile optimized micro-architecture including Intel Dynamic Power Coordination feature and Intel Advanced Thermal Manager. This platform will also feature very exciting next generation graphics aka Calistoga and new Wi-Fi LAN 802.11abg solution aka Golan.
Yonah platform: a year before launch
This platform will support new SSE instructions and will definitely offer notably improved performance, much better thermal management and much better thermal environment around components. From the network point of view it will also suggest better ways to balance the traffic. Also, it will offer longer battery life and more optimal usage algorithms. Napa platform is a premium digital office solution. It enables virtualization technologies that have been discussed earlier. Intel’s leadership in this field implies driving the rest of the platform to meet new industry standards. Such as power panels, battery capacity, lower power of SATA drives with Intel Active Matrix Storage technology.
In the digital office environment we have Zephyros system concept as an example. It provides full wireless connectivity, easy synchronization with other wireless devices, high performance, up to the mark video and audio quality. It is designed in super slim form-factor, features media access, dual core CPU, and Intel’s data and network security technologies.
Zephyros system
Another demo was dedicated to the performance differences between the notebooks running on the dual core 65nm CPU vs. single core CPU.
Multi-tasking on a multi-core 65nm system
We had two solutions side by side and we could hear interruptions of the radio playback when we had other applications downloading something to the hard drive in the background. A perfect example of the advantages brought to you by multi-threaded dual core architecture when you are running multiple tasks at the same time.
The third demo I would like to mention is called Embedded IT demo. It actually illustrated Intel’s concept for wireless security manageability.
The scenario in this case looks as follows. There is a management console with a list of all the clients in the Wi-Fi environment. In case the security system detects any malicious pattern on the network the potentially infected computer is automatically disconnected from the network until the problem is solved. It no longer has access to the network but can still be accessed and monitored by the managing console via wireless. We can enable the client and add it back to the network once the problem is eliminated.
Among a few examples of the advanced wireless features of the next generation mobile platforms within the digital home initiative Intel demonstrated what they call “on-the-go” solutions providing the same functionality and access to data when you are away from home. This solution would be regarded as a mobile entertainment PC. Within the mobile entertainment PC initiative there are two primary usage models that are most interesting right now:
Sync-n-go: it implies that you take the content with you. Intel suggests that you can use UPnP interface that allows downloading and sharing digital media content with other devices, which you will then use on the road for entertainment purposes.
EPC or “TIVO on the go” type of the device
The idea behind it is that you can use wireless connection to download the programs, MP3, DVD, or TV content to a portable Centrino powered device, with a HDD. Then you synchronize it via wireless with the TIVO device and get the content there, ready to go with you. For instance, if you have this TIVO or similar device built into your car (you could actually see a Land Rover with the built in “TIVO on the go” solution) you could take the content with you.
Outside In: implies that you have access to the content while away. Here Intel suggests using their own Orb service online, that creates a secure channel once you register, so you can view all you home PC contents anytime anywhere. The device is connected to the Orb server and provides constant and secure data transfer from your home system to your on-the-go device.
But let’s return to our discussion of the tendencies driving the mobile market growth.
This is the third tendency that drives the mobile market and that is a postulated first rule of mobility. In this respect we should first of all turn to WiMAX technology. I have already mentioned it in my yesterday’s IDF Day 1 Coverage, that WiMAX is growing rapidly. We have all that content ready to be unleashed to people with mobile devices. It is a great opportunity for everybody. According to Metcalfe’s Law, as devices are added to the network the value of the network is growing exponentially. It is true for WiMAX. In the mobile space the combination of two platforms, phone and notebook, and a combination of these with the wireless applications will work wonderful things and deliver the best to the consumers.
In his keynote presentation this morning Don MacDonald, Vice President and General Manager of Intel Digital Home Group outlined the major opportunities for industry players in the digital home arena as of today and tried to prove that despite the innovations on the technological and architectural levels (such as introduction of dual core technology) the digital home usage models are getting even more simple and easy to put into life.
Home is a really special place to each of us. Homes come in all shapes and sizes. And many of these are digital homes (right now more than 1 billion people use internet around the planet). Some definitions of a digital home require different terms. But Intel wanted to take a more pragmatic broader definition for a digital home, during that discussion they were intending to show us the possibilities in this global marketplace for the initiative like that. Of course, today they have to address some fundamental challenges about cost and performance of the systems classified as digital home solutions, and this is extremely relevant to the business community and idea of digital home.
Moor’s law works not only for the number of transistors per silicon, but it also works in a digital home space. For example, many of the Wi-Fi devices didn’t exist a few years ago and now they are growing in number. The consumer electronics industry has doubled in the last 4 years. It is about the existing devices that have been reignited by the digital revolution, driven by breakthrough technology in the high definition content.
Microsoft and Intel work together here. It is not only the hardware platform that is important but also the way the hardware platforms and solutions would communicate with the consumer and one another.
Also significant attention is paid to the price point of these devices, their power requirements and their slim and thin form-factor which is welcome in the digital home environment today, as well as security issues, which Intel’s new VT virtualization technology should take care of.
With the continuous evolution of the digital home concept more and more solutions which should fit in it get finally shaped up. And entertainment PC is definitely one of them.
This time Intel revealed those features and functions that an entertainment PC of today should boast thus setting s certain basic standard for devices of the kind. All hardware benefits combined together represent an ideal entertainment platform. According to Intel should be based on the dual core processor, which is new for this year. As for the mianboard, it will be built around Intel 945G Express chipset with the integrated graphics core and with the new ICH7 South Bridge, which will support:
You can see that there is DVI digital output. All today’s cards will have DVI outputs. The system will be supplied with a cable with a DVI connector on one end and a DVI or HDMI connector on the other. In fact, these two protocols, DVI and HDMI, are electrically compatible. HDMI does not have audio, though.
Also the card will feature analogue output, S-video or component and an antenna to catch your broadcast.
As I have already said above, this card will combine two devices on a single PCB, which will bring down the power consumption rate as well as the pricing point for the complete system quite noticeably.
Display is one the key points of the entertainment PC. Right now the quality of video is not good enough. The video performance should be as god as that of the mainstream consumer electronics devices, then the solution will succeed in the consumer electronics market where entertainment PCs are actually targeted. So it is important that selected tuner solutions have no compatibility issues with the entire platform. The most common tuner and display options as of today are the following:
All display and tuner cards are installed on risers. But there is no unified design for that, because depending on the cards selection you have different riser card design applied.
The form-factor for this platform will be extended BTX compliant chassis, which is smaller and quieter with standard fans and thermal module. In fact the chassis dimensions are in the first place determined by the power supply requirements and thermal module assembly (TMA) requirements. Depending on the component selection you can have two height options for the chassis. Take a look at this scheme to see what they are:
Here are a few picture of the displayed entertainment PC prototype:
Inside the prototype of the Entertainment PC
Tuner cards
Looks not bad at all, don’t you think so? Note that there is no additional vent holes on the front panel for cooling purposes, so that nothing takes away the typical consumer electronics look and feel of the product.
First of all what is dual core? What do we mean by dual core or multi-core processor?
We have two or more execution cores in the same processor package. So, on the lefthand side is the representation of the Pentium D processor, dual core processor based on the 90nm technology, with two independent execution cores, each with its own L2 cache. The picture shows that they are one piece of silicon, one monolithic piece of silicon with two dies mapping together. The mask is laid out, and when the wafer goes to the factory you can see that the two dies that are next to each other will be cut out as one piece of silicon and placed in the package.
The 65nm process will be used for multi-chip processors and instead of the two individual cores physically connected with silicon, there will be two independent pieces of silicon. They will be able to select those from anywhere on the wafer, even across wafers. But the selected two pieces of silicon should be of the same speed, to be put in the package.
When you have a chip in your hand you will not be able to identify by looking at it, whether it is a single piece of silicon or two pieces of silicon: electrically and physically it looks the same. But if you X-ray it, you will clearly see what’s in there. But whether it is one or two pieces of silicon it doesn’t actually matter: it makes no difference to the OEM or the end user.
The single piece of silicon or two pieces of silicon design choice depends on Intel’s design efficiency and manufacturing efficiencies and you will see this change over time.
This is a dual core solution. Each core has its own 1MB L2 cache and its own independent bus interface. Both cores have connections to the pins on front side bus. That gives us the total number of loads: three for the system bus, two for the processor, one for the chipset. Note that the bus runs at 800MHz.
The CPU supports 64-bit technology, Execute Disable Bit and is compatible with the LGA775 socket.
This processor will be available in Q2 2005.
Note that the multi-core version of Intel Pentium processor Extreme Edition will support HT technology, so you will have the ability to support 4 threads simultaneously.
The next generation processor will be manufactured with 65nm process and will have two separate cores. However, there are a few other changes. This Presler processor will have 2MB L2 cache, which is double the size of the cache compared with the Pentium D processor. It will be designed for the same socket, LGA775.
It will be available in the first half of 2006.
Intel will also have a single core version of Presler processor, manufactured with the same 65nm technology. It will support HT technology, 64-bit, Execute Disable Bit and will be designed for the LGA775 socket.
It will also be available in first half of next year.
It is a dual-processing server processor. It is based on the 65nm process technology. It supports HT, so there are 4 threads in this particular processor. It also features 64-bit support and Execute Disable Bit. The CPU will be designed for the server based LGA771 socket. The bus will allow only three loads.
For multi-processing systems Intel will have the Paxville processor. It will have is two independent cores and two independent L2 caches, but there will be one difference here: it will be designed on a single piece of silicon. So, the two cores will share one bus interface. As a result, the bur will allow only two loads.
This solution will be available the same time frame as Dempsy processor, namely in Q1 2006.
The dual core Itanium processor will support 4 threads and will be designed with 90nm technology. It’s got two independent L2 instruction caches each 1MB big. And there will be two L3 caches. It will be designed on a single piece of silicon, but there is no single line you can draw to cut the two cores apart, like we could do on the previous generations of CPUs discussed above. It is pretty highly integrated: we have caches on the top and bottom, and the execution cores are kind of joined together. This die has 1.7 billion transistors which is a huge number. (Compare with the 29,000 transistors in the 8088 processors dating back to 1979, when IBM launched their first PC. Pretty impressive, eh? :).
It will be available in Q4 2005.
This is a schematic representation of the pipeline and the architecture. The instructions are coming in and they get assigned to the floating point unit or the integer unit. There is also an independent L2 cache and the bus interface. This is what we have today, and everybody is familiar with this.
For the dual core processor everything will be duplicated. It will have two pipelines, two floating point units, two integer units, two caches and two bus interfaces. And these two cores will be put together in one single piece of silicon as a pair
If we look at the Presler, the only difference from the above described scheme will be the availability of two independent cores within the silicon.
And in case of Paxville processor, we will have a shared common bus interface.
Intel 955/945 Express chipsets will be designed to support new dual core solutions. This is how the whole thing should actually work.
When the operating system boots up it has to know which core is Core 0, the boot strap device, and which core is Core 1. And that’s defined by the way the bus request lines are routed on the sub-straight of the package. So when the processor powers up, the BREQ lines are set appropriately and Core 0 is identified as boot strap device.
Note that contemporary Intel 925 and 915 chipsets do not support dual core, multi-core or multi-processing systems. So if you happen to install the Pentium D processor in one of these older platforms it is not going to work. There will be no power sent to the processor. So, no harm is going to be done to either the board or the processor, and you can take it out and install into the right platform and it will work as expected.
The Dempsy dual-processor platform supports 2 sockets, and as you may notice on the picture below there are two independent bus interfaces.
There are two completely separate trace routing procedures for each socket, because it gives better optimization and more efficient data transfer rates between the two cores and memory. Number of loads on the bus equals three on each bus. If both sockets are assigned to the same bus there will be 5 loads and the bus may not work correctly.
The architecture for the Paxville multi-processor is very similar: there are two sockets per bus, two independent busses on the E8500 chipset, but here it is possible because the bus interface can be shared between the two execution cores.
This bus allows the total of three loads, but you can put 4 processors in the system. Note that these trace routers could be somewhat longer, because there are 4 processors in the system, so its is important to keep the number of loads per bus equal to 3.
So, which device becomes boot strap device, will depend on how many processors are installed and which socket they are installed into. When the system powers up each processor arbitrates with the chipset to see which core is Core 0, the boot strap device. With the time you could change the system configuration. However, the boot strap device has to be the earliest revision of the processor. So if there is A1 and B1 processor in the system, then the A1 has to be the boot strap device because the OS will assume that all other processors in that system have the same feature capabilities as the boot strap device. Every time the BIOS will basically be checking other processor versions and reassigning the boot strap device to the earlier version if necessary.
Here is the processor architecture scheme with all the major components. Now let’s see how the HT technology will work on different dual and multi core processor designs
If we run an integer thread through the Pentium 4 processor without the HT support, we will see that it goes down the pipeline and gets assigned to the integer execution unit. All the instructions will follow that path.
If we run floating point thread through the same processor the same thing will happen with that only difference that it will go to the floating point execution unit.
Now let’s take a look at the same processor with HT and both: integer and floating point threads running at the same time. They will both go down the pipeline and get assigned to the appropriate execution units. You get more work done because you are utilizing resources in a more optimal way.
If we have two floating point threads in the HT enabled processor they both get down the pipeline at the same time and get assigned to the execution unit and if they are using exact same code they will be competing inside the execution unit for the resources. In this case there will not be much of the performance improvement, but this is not necessarily the case, because FP instructions might be using different resources inside that unit.
Now let’s take a look at the Pentium D. It does not have HT, but it has two complete execution cores with two integer engines, two floating point engines, etc. And when we have the same two floating point threads they get their own processor floating point unit each and the processing is done faster than in case of a single core processor with HT technology support.
The extreme Edition multi core processor that also has HT can run 4 of these threads at the same time and we will be getting even better performance improvement. But of course, the performance will depend on the system setup, applications that you are running, the amount of supported memory. This is just a general concept:
According to Intel, Microsoft is going to license Windows for dual and multi core systems on the per socket basis. No matter home many cores or threads are there: there is going to be only one copy of the XP Home for that processor. The story is similar for Linux, it is also going to be licensing on a per socket basis.
In terms of support by the applications we can say that any application that supports HT will also support multi core.
If the application is not written for multi core it will still run fine, but you will not be able to take advantage of the performance capabilities.
All the major OS are ready for multi core applications. Intel claims that there is lot of software out there already and there is more to be announced.
At Intel booth called Multi-Core Zone they were demonstrating a game based on Unreal 3 gaming engine which was running on a system equipped with dual core 3.2GHz Pentium Extreme Edition processor supporting 8 threads.
Game based on Unreal 3 engine running on new multi-core CPU
Also I got the opportunity to see side by side comparison of the performance demonstrated by two systems: the first one was built with multi-core Intel Pentium Extreme Edition 3.2GHz and Intel 955 chipset (left), while the second one was built with a single core Intel Pentium 4 Extreme Edition 3.7GHz and Intel 925 chipset (right).
In both games I saw, which were running on dual core hardware the graphics quality was very fine and smooth, and the physics models were very realistic. Well, the visual test was highly positive, but I wouldn’t draw any conclusions about the performance of the new dual and multi core solutions in the new games until we get a chance to really investigate the performance advantages in our labs.
From the thermal management prospective Intel did introduce the same features as those that we have already seen in the recently announced Pentium 6xx processors.
You should keep I mind however that power dissipation of each processor is determined by a number of things and one of them is the type of instructions that are run on that particular core. So there is no relation between the two cores as far as the amount of power to be dissipated by each of them is concerned. They can both be at the maximum or they can both be idle, or in between. And this will change continuously because the instructions will change continuously.
The fan speed control and temperature monitoring will be managed by an on-die thermal diode. The monolithic processors in the desktop field will have a single diode. For the server environment Intel will be providing two thermal diodes, because servers need to monitor more temperatures in the system and more areas.
Among the features already introduced in the 6xx series CPUs are:
We have already discussed them in detail in our article called Intel Pentium 4 6XX and Intel Pentium 4 Extreme Edition 3.73GHz CPU Review.
You should however keep in mind that there are specific voltage restrictions that would apply to the dual core processors:
HyperThreading is 2 threads running on the same execution core that share processor resources, execution resources and cache hierarchy.
Dual Core is defined as 2 execution cores in the same processor package
Multi-Core is two or more execution cores in the same processor package.
The only thing that is shared in the dual core environment is the system bus, they don’t share the cache, they have their own execution engines, and in terms of software and hardware this is very similar to dual-processing: whether you have two single cores on two sockets or one socket with 2 execution cores, it looks the same and behaves the same as dual-processing.
Dual-Processing or Multi-Processing is defined as 2 or more processors in the same system. And the only thing they share is the system bus and the benefit comes from the use of more sockets which multiplies the execution resources and you get higher performance.