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Ring-Bus Memory Controller: Implementing 512-bit Bus

The memory controller has been considerably improved in the new GPU generation, in an evolutionary way. The first generation of ring-bus controllers used to have two unidirectional 256-bit buses in the fastest version, but the R600’s controller uses four such buses for a combined 1024-bit ring bus and does not use classic-topology elements which were present in the memory controller of the Radeon X1000 series. Without a single command center, this controller is a fully distributed solution.


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According to ATI’s diagrams, the ring has four Ring Stops that receive and transmit data from the core and memory. The fifth stop is a joint point where the R600 connects to the PCI Express bus (required for HyperMemory technology). It is logical to suppose there are not 4 but 16 stops because there are 16 BGA memory chips with a 32-bit interface each. AMD’s diagrams show, however, that the R600 uses full-duplex dual-channel memory controllers (termed Ring Stops), which allows addressing 16 memory chips.

Four such channels make up a 512-bit external access bus – for the first time in the consumer 3D graphics world! This provides a very high memory subsystem bandwidth which is so demanded today, in the era of high display resolutions, extreme antialiasing levels and HDR rendering.

 
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