X-bit labs

DDR vs. DDRII: Fight! (page 2)

Category: Memory

by Victor Kartunov

[ 05/19/2004 | 11:30 AM ]

In other words, the elementary DRAM cell remains the foundation of all the variety of modern memory types. Thus, all modern memory types inherited both advantages and shortcoming of DRAM: the need for regeneration and the operational frequency ceiling. Talking about the last parameter, you may notice that the clock rate of DRAM has only changed by one factor throughout its long history, while other PC subsystems have progressed much faster. This is only because the classic organization of the memory cell makes it difficult to increase its clock rate. In fact, the frequency grows only along with the reduction of the geometrical dimensions of the cell due to the constantly improving technological process.

Today, specially culled (but produced industrially) memory has a cell frequency of 275MHz (I mean DDR550 that some manufacturers like Hynix have announced). This method of progressing involves much spending into the transition to a thinner tech process. In fact, one up-to-date semiconductor factory costs over $2 billion, and that’s not the end. Note also that the real frequency of memory cells is not 550MHz as the marking suggests but twice lower. We’ll clear this fact out shortly.

Thus, we’ve got only one way left – to enlarge the memory bus. Again, our opportunities are limited: today, standard platforms use a dual-channel 128-bit memory bus. Designing, wiring and producing mainboards with such a bus is a much more complex matter than doing the same for the 64-bit bus. And wiring a 256-bit bus is so costly that it makes sense for servers only. Of course, this situation changes with time, but today such mainboards would be too expensive for the mass market.

So we find ourselves in a kind of deadlock. Memory cells don’t grow in frequency and the memory bus is not easily expandable. Where’s the way out?

There’s a method once suggested by Rambus. The idea can be expressed in one word: multiplexing. We can describe it in more detail, too.

SDRAM (Synchronous Dynamic Random-Access Memory)

First, let’s recall the operational principle of the now-obsolete SDRAM. In fact, it consists of an array of cells, Input/Output buffers and power/regeneration circuitry. The last item is of no importance for us for now.

All three subsystems work at the same sync frequency – that’s where “Synchronous” comes from. Let this frequency be 100MHz and the bus width – 64 bits, for example. The memory data are taken to the I/O buffers and then to the memory controller. A memory module on such chips is known as PC100 memory and has a bandwidth of 800MB/s (100MHz x 8 bytes or 64 bits). The data is transferred once per clock, on the rising edge of the clock signal.