DDR (Double Data Rate SDRAM)

DDR has its name because it can output data twice faster than SDRAM of the same frequency. That is, twice per clock cycle, on the signal’s rising and falling edges. But these data should be taken from somewhere, yes? The developers went for a trick: the memory cells are working at the same frequency, but the internal bus is wider to boost the data-transfer rate inside the chip. In other words, the internal path from the array of cells to the buffer is twice wider than the external path, from the buffer to the controller. The resulting frequency of the data-transfer rate from the buffer to the controller is twice higher than the frequency of the memory cells. That is, the data go from the cells along a wide bus, but then go to the controller along a narrower, but faster bus.

Let’s see it in numbers. Let the width of the internal bus of the chip is 32 bits and the cell array works at 100MHz. Then, with SDRAM, the buffer transfers data along the external 32-bit bus at the same 100MHz frequency. There’s no change in the data flow along all the way. Data are read from two chips at once and the whole module is 64-bit.

DDR is another matter. Now we have an array of memory cells that pumps data along the internal 100MHz 64-bit bus to the I/O buffer (or the level amplifier). But the data go to the controller along a twice as narrow, 32-bit bus. On the other hand, now data are transferred twice per clock, along the rise and fall edges of the signal. That is, the resulting data-transfer rate is twice as high as the original frequency of the memory cells. Now we have a simple and evident equation: the data flows slowly along a wide pipe, but then get into a twice-narrower pipe and start flowing faster. We have a kind of “Bernoulli’s principle” applied to computer science. The module is 64-bit, so two chips of the module are being read simultaneously. I don’t now pay attention to certain peculiarities like that the address can be only set for one memory bank at one moment and the other bank cannot get the address sooner than in a clock cycle.

Such memory was named DDR200 (by the resulting data-transfer frequency) or PC1600. Accordingly, DRAM cells in DDR266 memory work at 133MHz, in DDR333 – at 166MHz and in DDR400 – at 200MHz. Currently mass-produced DDR SDRAM (I don’t count in “memory for overclockers”) has grown to a frequency of 550MHz – that’s why I wrote 275MHz above, talking about the frequency of the array of DRAM cells. But it’s very problematic to raise this clock rate further. The industry may overcome the barrier of 300MHz, but what’s of it? The DDR technology has no performance reserve. The industry needs a new memory standard that would ensure a stable frequency and performance growth for some time more.

DDR2 memory is going to be the answer.