The key principle of DDR2 is easy to understand once you learn what DDR SDRAM is. Like with DDR, the internal bank issues data to the I/O buffers along a broad 64-bit 100MHz internal bus. But now the data go from the buffer at a faster and narrower bus (16 bit, 200MHz), which uses the Double Data Rate trick. Thus, we achieve a resulting data-rate frequency of 400MHz! Accordingly, the 64 bits on the module output are made up by simultaneous transmission from four banks. Such memory module goes under the name of DDR2-400 – the marking system is similar to that of DDR, telling the resulting data-transfer rate to the memory controller.
Picture taken from http://www.lostcircuits.com/
Thus, for one and the same frequency of the array of DRAM cells – 100MHz – we have different memory module bandwidths. It is 800MB/s for SDRAM and 1600MB/s for DDR SDRAM and 3200MB/s for DDR2 SDRAM! Thanks to multiplexing, the memory module has a higher bandwidth although the memory cells work at the same low frequency. That’s what we need to be able to fetch data for the processor.
This is the main idea that distinguishes DDR2 from DDR. However, the difference between the two memory types is not only in their bandwidth.
Besides bandwidth, there is an important characteristic called latency. As I said above, the memory cell is not always available because of the refresh procedure. Moreover, even if the cell is available, it’s not possible to get its contents instantaneously: there are other types of latencies such as the time it takes to set up the address of the column or row, the minimum time between setting different addresses. Such latencies are not intrinsic in any specific memory type; they are always here because all memory types use the same elementary DRAM cell.
Let’s now see what we have with latencies. Let the cell array in the above example works at 2-2-2 clock combination. Since the array works at the same frequency in all cases, all modules will have the same latencies (I speak about PC100, DDR200 and DDR2-400). Only the bandwidth differs. By the way, the 2-2-2 combination means: CAS Latency, RAS-to-CAS Delay and RAS Precharge time. The first number is the latency of extracting the column address, the second is the latency between the addresses of the row and column and the third is the time it takes to charge up the cells in the row before giving the data out.