X-bit labs

DDR vs. DDRII: Fight! (page 7)

Category: Memory

by Victor Kartunov

[ 05/19/2004 | 11:30 AM ]

This additional latency was introduced in DDR2 to solve this problem. Its point is in transferring the read command automatically to the next clock in case of conflict. Thus, we seem to get data a clock cycle later, but there are no bubbles in the data stream and the efficiency of the memory subsystem is increased.

The next divergence between the memory types is in DDR2’s ability to do Variable Write Latency. DDR always has a write latency of 1T. This time is dictated by the specification and cannot be changed. For DDR2, this write latency depends on the read latency and equals write latency minus one clock. For example, the read latency being 7 clocks, the write latency will be 6 clocks. This sounds terrible compared to 1 clock for DDR. In reality, it’s not that bad, because the write procedure with DDR requires some special preparation, unnecessary in DDR2. So there is a difference, but it is smaller than may seem. The resulting write latency of DDR2 is about three times higher than with DDR.

Conclusion

Let’s summarize. DDR2 memory comes in 240-pin modules of the same length as the ordinary 184-pin DIMMs (the pins will be smaller). The modules are characterized by their potential of reaching higher operational frequencies. Moreover, they contain certain improvements that allow for a higher efficiency of the memory. However, besides evident advantages, the memory has drawbacks: first, it has much higher frequencies at the same interface clock rate. Second, write latencies grow considerably. Third, this memory will have a higher cost due to its much more expensive packaging. Other differences are listed in the following comparative table:

* Megabit/pin/sec
** The specification originally described a packet length of 4QW, but later added the 8QW mode, proposed by Intel and Samsung.