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Memory Sub-System Synthetic Benchmarks

First of all we are going to check out the synthetic tests of the memory sub-system performance. We will test the actual bandwidth and latency using Cachemem benchmark built into AIDA64 utility.

The obtained results reveal a few interesting things. First of all, I would like to point out right away that there is a significant difference in actual memory sub-system speeds between the memory modules with different frequencies and timings. By simply increasing the DDR3 SDRAM speed from 1067 MHz to 2133 MHz we stimulate a gigantic 60% increase in practical bandwidth. We haven’t seen anything like that in systems based on other processors, which indicates clearly that there are really no serious bottlenecks on the bus fragment between the processor cores and system memory.

Secondly, it is quite symptomatic that not only the read speed, but also the write speed depends on the memory modules frequency. There was no dependency like that in the previous-generation systems at all, or it was really minimal. This peculiarity of the Sandy Bridge memory controller will also contribute to the system performance gain upon increasing the memory frequency.

Thirdly, I have to say that DDR3 memory modules frequency has a greater effect on the memory sub-system performance than their timings. In fact, lower timings produce just a little lower practical latency, while by simply setting the memory frequency one 266-MHz increment higher we can easily outdo the effect from lowering the timings.

As a result, we can conclude that it definitely makes sense to use overclocker memory in LGA1155 systems. However, we should have our preferences set for higher frequency rather than lower timings. Anyway, now we are talking only about the results of synthetic benchmarks, which serve to estimate the system performance during work with the memory.

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