by FastSite
02/16/2003 | 12:00 AM
As soon as we start talking about computer memory, two key performance-related problems arise: bandwidth and latencies. It's just like a racing car: we want it to speed up fast and also have high full speed. Ideally, the two parameters must match each other or you will lose either at turns or at straight parts of the track. As we are so unlucky to live in a non-ideal world, we often have to compromise and choose one of the two parameters to improve first.
There is a kind of division of labor in the industry depending on what company engineers consider the most horrible DRAM vulnerability. For example, Ramtron blames latencies and promotes ESDRAM through its affiliate company Enhanced Memory Systems. Kentron stands for the opposite side and its approach we are going to discuss today.
They start out from the obvious premise: modern CPUs put much higher demands onto the memory subsystem than it can meet. Today's 533MHz FSB of Pentium 4 CPUs delivers 4.3GB/s bandwidth. The upcoming 800MHz FSB will notch 6.4GB/s. At the same time, the maximum bandwidth of a standard DDR module is 3.2GB/s. This is not enough even for the current system bus and we can't hope for any significant advances in the near future.
Now, let's turn to the basics and recall what this memory bandwidth actually is. Luckily, you don't have to take a course in math1s to calculate the thing:
Bandwidth = Bus width x Bus frequency x Number of packs transferred per clock cycle.
For example, in case of PC2700 DDR, the DRAM chip core frequency is 166MHz, the memory bus width is 64bit (or 8Bytes, if you like) and two data packs are transferred per clock. In total it makes 166x8x2 = 2700MB/s.
So, there are three ways to increase memory bandwidth that occur to us on the spot. They correspond to the three parameters of the above-described formula.
The most straightforward way is to increase memory chip frequency. Well, it's quite achievable in a certain way. Manufacturers have already overclocked DDR SDRAM to 4GB/s or 250MHz (compared with the standard 166MHz). But practice shows that the end-performance of these solutions is at most no better than that of standard-frequency modules. It comes as developers have to increase latencies along with the working frequency in order to provide acceptable operation stability. So, these modules can't boast high performance while they do "boast" notably higher price.
By the way, the problem with this approach is also valid for DDR-II. That's why DDR-II bandwidth and frequency won't be too much higher than those of DDR, although it's a long time yet for such chips to come into mass production.
The second, more refined way: to broaden the bus so that it would be possible to transfer more data per clock. Let's make it 128bit wide, instead of the today's 64bit. It's quite reasonable, too. Moreover, as the broader bus means using several parallel 64-bit channels, there would be no problems with latencies here. Every channel would work in its nominal mode. But…
The price of such a solution becomes the negative factor. Of course, we need at least two DIMM modules for the two channels to work effectively (which already means higher cost of the solution). We also need 128 signal lines instead of 64 and a memory controller with more pins (i.e. more contacts by the chipset North Bridge). On the whole, the layout and components mounting grow much more complex, so we need expensive 6-layer PCB instead of a cheaper 4-layer one to ensure proper signal stability. It's all right with servers and workstations, but not in case of mainstream PCs where the price is very important.
And the third possibility left is to increase the multiplier, which builds one 64-bit data pack per clock in case of SDRAM and two in case of DDR SDRAM. Overall, we only need to make some changes to the controller chip and memory chips. That is the solution promoted by Kentron. The company claims it to be both: simple and low-cost. Let's check it out.
First of all, let's get to know the basics of how this memory type works. As it is based on DDR, we will just point out its differences from DDR.
As is known, the number of banks, i.e. logical units, which are used by the CPU for chips access, is an even number. QBM (Quad Band Memory) technology unites these memory banks into pairs. The signal of the first bank is in phase with the controller clock, while the second bank has a phase difference of 90 degrees from the first clock. Here we will need a helping hand from a special switch called QBM10. It will identify which of the two banks is being accessed by checking the phase.
Delving deep, QBM10 is a combination of a 10-bit 2-to-1 switch and a 10-bit register, which distributes the controller workload more evenly, reduces the execution time of some operations in the work cycle and improves charge/capacity ratio. There are also some nice trifles like the doubling of the correctness window during writing operations, that is the time interval when the data sent to the memory module by the chipset are still considered correct.
In fact, all these functional units are quite simple, so QBM10 is simple and not expensive, too: 48 pins, 7x7mm area. It's just a small drop lost against the background of a TSOP-packaged DRAM chip. On the other hand, eight switches like that plus an additional frequency generator are necessary for a standard unbuffered DIMM module. So, it all may amount to a high total. But we will talk about the price of the solution later on.
Of course, we can't move along just putting switches into memory modules. Chipset's support is also required and this is where similar initiatives from various companies usually tripped over.
Intel still plays the main role here holding a considerable share of the chipset market. Moreover, Intel has always been advancing the industry. The Rambus affair is not enough to break this tradition. But, Intel isn't eager to promote QBM. Among well-known manufacturers, only VIA and SiS support this memory type. In fact, SiS is far less active than VIA.
Actually, VIA's position is quite understandable. The company doesn't sit at the curbstone of the world progress, but watches closely all emerging technologies. VIA just sticks to another ideology: they don't push ahead and put up industry milestones, but develop available technologies to their maximum price-to-performance ratio. That's what we saw when Intel staked on Rambus, and VIA - on PC133 SDRAM.
Today both companies unanimously supported PC3200 DDR SDRAM. Of course, there is a question of where to go now. This memory type will last quite long with Athlon XP, while Pentium 4 lacks the bandwidth already. The first possibility of the three, which we have already discussed above is simply unreal: DRAM makers just can't increase the frequency any higher because of their current technological capabilities. Intel chose the second way and has already started shipping dual-channel DDR chipsets. Well, the company had already gone this way before in its i840 chipset, although it supported dual-channel Direct RDRAM.
This approach seems advantageous for today, that's why SiS and VIA also started producing dual-channel DDR chipsets. Firstly, two PC3200 channels exactly meet the requirements of 800MHz FSB for future Pentium 4 (that's exactly why Intel reconsidered its attitude to this memory type): 8x800 = 6.4GB/s. Secondly, there is no need to push the memory makers any more: no new controllers, no changes of the technological process are necessary. Moreover, all already manufactured PC3200 modules are also guaranteed to provide the desired 6.4GB/sec.
This approach has no future perspectives. Four-channel configurations seem senseless from the economical point of view, while FSB frequency of Pentium 4 is unlikely to grow higher in near future, at least not until DDR II is ready.
Of course, this approach is not free from some drawbacks. In fact, there is only one drawback: the price. Mainboards will cost more and the user will have to buy two memory modules, since single-module configurations will no longer work fine. It's hardly a nice thing, but the inevitable price reduction will eliminate this disadvantage almost completely.
The upcoming VIA PT800 chipset supporting QBM will hardly be a better-value solution. QBM PC3200 modules deliver the same 6.4GB/s in one-channel configurations. The mainboard can feature simple, 4-layer design. The price of the chipset isn't greatly affected by integration of the QBM logic. But the memory modules themselves will cost a lot. By preliminary estimates, a QBM module will cost about $15 more than a DDR module of the same capacity and frequency. This may definitely kill other cost advantages.
Kentron appeals to the future and is quite reasonable about it: PC6400 DDR II modules will come into the market around the year 2005 and won't be compatible with current DDR modules. Take their pin difference as an example: 184 against 232. Kentron offers the same performance, but today and using current infrastructure. There are no compatibility issues: mainboards supporting QBM will also work with ordinary DDR DIMMs.
There is one more thing to be mentioned: Kentron's proposal also promises latencies reduction and stability growth thanks to QBM10 switches. The sample models show that QBM memory timings are at least no worse than those in DDR II, while signal lines volume is considerably reduced compared to current DDR modules. It means higher capacities and more DIMM slots than usual.
Overall, we have got an ambiguous situation. There are two approaches similar from the price point of view, but differing in everything else. The dual-channel DDR will provide 6.4GB/s bandwidth with current mass production modules, but it's impossible to increase the bandwidth any higher. QBM will yield the same 6.4GB/s, but with some future perspectives: two channels will deliver 12.8GB/s at a reasonable price. But for QBM to become popular, it's necessary that at least several big manufacturers supported this standard. And they don't really like experiments like that.
On the other hand, the situation is changing somehow. Remember the last Kingston's move with its overclocked DDR modules? The company has always been a pattern of solidity, but business is business: make money the way you can.
Kentron promised to sample 4.2GB/s QBM modules (based on PC2100 DDR) in December, with mass availability in the first quarter of 2003. Then it promised to launch PC2700 based 5.4GB/s models together with the arrival of Pentium 4 supporting 667MHz FSB. Now the plans have been corrected and Kentron promises to provide enough 6.4GB/s (PC3200) QBM modules in the second half of 2003. So, let's wait, although…
The short list of QBM Alliance members includes only one module maker. It's PNY Technologies, which is not a prominent player in the DIMM modules market. That's all. We can hardly hope for any changes in the near future. There are no serious reasons for DIMM makers to support QBM. They can't follow VIA in the Pentium 4 chipsets market: we all know how "strong" VIA feels there.
As for Intel, it all looks quite clear, too. The company has made its choice: they decided to support the dual-channel configuration. Intel won't support any of VIA's initiatives (and QBM is now VIA's initiative as well as Kentron's). And moreover, Intel's approach is quite competitive now, so the industry will preferably support it.
The summary is simple: QBM is an interesting, but doomed idea. In all probability, it will follow the fate of another interesting technology, VCM SDRAM, proposed by NEC, but completely ignored by the industry.