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From Yonah to Merom: What’s New?

Although Intel tries to convince unsophisticated users that processors with Core microarchitecture are further evolution of the mobile microarchitecture as well as of NetBurst microarchitecture, this statement arouses certain doubts. We believe that Conroe, Merom and Woodcrest processors hardly inherit anything from NetBurst, and Core microarchitecture should be regarded as the next step in the Pentium III – Pentium M – Core Duo evolution chain. This also results from the fact that the new CPUs feature short 14-stage pipeline and hence are not destined to hit any sky-high frequencies. Even the name of the processors based on new microarchitecture suggests the same: Core 2 Duo (the same name for desktop and mobile solutions).

We have already devoted the entire article to the details of the Core microarchitecture, so please feel free to check out our review called Getting Ready to Meet Intel Core 2 Duo: Core Microarchitecture Unleashed. However, when we discussed the peculiarities of Intel Conroe processors that are architecturally the same as our today’s heroes, the mobile Merom CPUs, we didn’t intend to compare them against Core Duo (Yonah). But today we are about to do it.

Let’s take a look at the improvements in the new Merom processor that are absent by Yonah. Although before we start let’s pay special attention to the similarities that make these two solutions somewhat related. The first thing that catches your eye right away is the fact that both – Yonah and Merom – feature dual-core structure with shared L2 cache memory. Both processors use Intel Smart Cache technology that allows both cores to use the same areas of the cache-memory and engage the amount of memory according to the current needs. Note however, that the size of available L2 cache memory can be different in Yonah and Merom, though it doesn’t affect the concept.

Moreover, both processors feature identical L2 cache memory that implies not only the same capacity, but also the same structure and organization. There are 32KB allocated for the instructions and for data.

The instructions execution scheme is also similar by Yonah and Merom. Both processors feature the execution pipeline of almost the same length, although the pipeline of the newer processor is 2 stages longer. This comes from the significant differences between these seemingly very similar processors. The engineering team that designed Merom introduced a lot of improvements for this new processor. The main improvement is certainly the support of 64-bit extensions of x86 Intel 64 architecture and the so called Intel Wide Dynamic Execution technology that implies that there are much more decoders and execution units in the new processor core.

I don’t want to overload my story with technical parameters, so here is a comparative table that will guide you through the major micro-architectural specs of the Yonah and Merom processors:

 

Intel Core Duo (Yonah)

Intel Core 2 Duo
(Merom)

Cores

2

2

L1 data cache

32 KB

32 KB

L1 instruction cache

32 KB

32 KB

L1 cache latency

3 cycles

3 cycles

L1 cache associativity

8-way

8-way

L2 cache size

2 MB

2/4 MB

L2 cache latency

14 cycles

14 cycles

L2 cache associativity

8-way

8/16-way

L2 cache bus width

256 bit

256 bit

Pipeline

12 stages

14 stages

x86 decoders

1 complex and 2 simple

1 complex and 3 simple

Micro-ops fusion technology

Yes

Yes

Macrofusion technology

None

Yes

Integer execution units

2 ALU + 2 AGU

3 ALU + 2 AGU

Load/Store units

2 (1 Load + 1 Store)

2 (1 Load + 1 Store)

FP execution units

FMUL/FADD

FADD + FMUL + FLOAD + FSTORE

SSE execution units

1 (64-bit)

3 (128-bit)

SSE instructions support

SSE3

SSE3+

Intel 64 support

None

Yes

Production technology

65 nm

65 mn

Transistors

151 mln.

291 mln.

Die size

90.3 sq.mm

144.9 sq.mm

Note that besides the larger number of decoders and execution units, newer Merom processors also boast Macrofusion technology support. This technology allows increasing the instructions decoding speed by 1 instruction per cycle if the code has branch prediction algorithms. So, processors with Core microarchitecture can definitely process more instructions per clock cycle than the previous generation Yonah CPUs, at all stages.

As you can see from the table above, another advantage Merom has over Yonah is faster operation with SSE and FP instructions. It is achieved thanks to additional corresponding functional units as well as to expanded length of SSE operands.

Among other advantages of Merom processor that aren’t listed in the table above are greatly improved prefetch algorithms as well as memory disambiguation technology that makes out-of-order commands execution even more efficient.

In other words, despite significant similarities between Merom and Yonah processors, the former represents a tremendous step forward from the micro-architectural standpoint. Therefore, theory suggests that Merom should be a significantly faster mobile solution that Yonah. However, the performance is not the only thing that matters for notebook CPUs. The second most important aspect is power consumption that directly affects the battery life of the platform. That is why before we draw final conclusions regarding the prospects of the new Merom processor in the mobile segment, let’s address some of its other features as well.

 
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