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Mobile dual-core processor manufactured with 65nm technology aka Yonah, which I have already talked about during the Napa platform discussion, will feature Intel Smart cache. Smart cache means shared cache between the two cores. Since we have two cores and we have a single bus, there will also be shared single bus interface. This way both cores can share the same copy of data from the L2 cache. Besides that, the L2 and data cache unit feature improved pre-fetches, i.e. we can do pre-fetches on the per-thread basis, thus ensuring better bus utilization. It also has bandwidth adaptation buffer, i.e. each core takes 4 cycles to adapt.

The difference between independent and shared caches is the following. In case of independent caches the data is transferred from one core to another via the FSB. In case of shared caches the data is transferred directly between the caches, you avoid the bus traffic and synchronization time to get on the bus. This is important for multi-processing systems, because this way you reduce the number of bus cycles involved.

As you can see from the roadmap this solution is also coming in Q1 2006.

For the DP (dual-processor) server market Intel will have DP Dempsey based on 65nm technology. It will have a 2MB L2 cache, ad can run 4 threads simultaneously, as supports Hyper-Threading. The anticipated schedule for this processor is also Q1 2006.

DP and MP Paxville will be made with 90nm process. They will have single bus interface running at 667MHz although there will be independent caches, not shared ones. They will also support Intel Virtualization technology.

These CPUs are coming out in H2 2006.

DP Sossaman will be based on the Yonah core and will be targeted at the server applications, where higher density smaller form-factors are of more importance. This CPU will feature shared L2 cache just like Yonah. According to the roadmap, we can expect them in H2 2006.

Multi-processor Tulsa manufactured with 65nm process will be equipped with 16MB large L3 cache, and will be used in those platforms where large caches ensure significant performance improvement.

For the Itanium 2 family there is Montecito, a CPU composed of 1.7 billion transistors. Each core has its own 1MB L2 and 12MB L3 cache, that makes the total amount of cache memory equal to 26MB.

This solution should be available this year already.

I will continue reporting the latest news from IDF tomorrow, so stay tuned for more news!

 
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